override UVM phase?
I just wonder if it is possible to override a build phase from uvm_driver? Seems there's only way is to override driver type/instance, but not phase. thanks, Jennifer,
View Article"Mixin" classes - parametrizing the base class
Hi UVM and SystemVerilog users, I've stumbled upon a particular pattern of writing a "utility" class, which I have called "mixin". class derived_class#(type BASE=base_class) extends BASE; .......
View Articleprint internal variables of property in sva
Hi , Could you please help me on how to print or display internal variables of property used in sva Regards, Pavan.
View Articlewho can interpret use of soft constraint ?
Hi,I have such a question https://verificationacademy.com/forums/uvm/how-use-soft-constraint who can help me ? thanks /wszhong
View ArticleHow to do multiple writes using uvm_hdl_force
Hi, I my using uvm_hdl_force("path",data) to configure the registers of the design. But the problem is they are large in number so i want to loop them in. for(int i=0; i<8; i++) begin for(int...
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How to override set_timeout
Hello All, Please help me : I have different tests requiring different timeouts, let say: 1. Test1 - timeout 100ns 2. Test2 - timeout 100ms 3. Test3 - timeout 1s In the test base I have...
View ArticlePointer passing across multi-language boundaries - SC<->SV
Hello All, A professional collegue asked me this question today, at that time I missed to answer. But assured him that we will discuss this over accellera. So the answer is UVM_TLM_GP, it is...
View ArticleCan we perform UVM_REG read/write access based on Address?
Hi there From the UVM users guide, a register read access can be executed as reg_model.BLK1.REG_FILE1.REG_1.read(status, rdata); But this mandates us to know the hierarchy of the register...
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uvm_tlm_analysis_fifo issue
Hello All, I am facing a acute problem: Using a uvm_tlm_analysis_fifo as: class bla_bla extends uvm_component uvm_tlm_analysis_fifo (my_packet) analysis_fifo; my_packet get_my_packet ; // other...
View Articleuvm_hdl_force error
Hi, While doing force using "uvm_hdl_force", i am getting the below error and the specified memory location is not written with that value. But it works using "force". Any solution to this. ERROR:...
View Articleuvm reg limitation
Hi, I there a limitation to the number of registers that can be handled by uvm register model? if yes, whats the count. QW
View ArticleIs there any obligation in using dynamic delay while starting the sequences
Hello All , I am wandering that why virtual sequence not allowing me to implement delays : Consider the following three cases - 1 . //-------------------------------------------------------------...
View ArticleConfigure DUT ports from outside agent
Hi All, I am learning UVM at the moment and I am working on an I2C slave monitor. I want to put multiple I2C slaves on a bus, each slave will have a dedicated agent. One of these agents will be...
View Articleuvm_send is blocked even after driver executes item_done
Hi All, I have a sequence sending a created and randomized item using `uvm_send. The driver receives an item using try_next_item. Upon receiving, it drives the item and calls item_done. Using debug...
View ArticleHow to use SVA check different clock delay
Hello, I would like to check tiny delay b/w clk1 and clk2.(delay inside [1.2ns : 3.2ns]). Can this kind of check be implemented by SVA? How record 2 timestamp in one property? @(posedge...
View Articlehow do we sort the UVM_REG space based on address?
Hi there We want to traverse through all registers present in a UVM_REG_BLOCK based on increasing address. We have the following pseudocode: model.NTB_DB.get_registers(total_regs_ntb); foreach...
View Articleconditionnal import package in SV
Hello everyone, I want to select package depending of parameter. I have the same parameters which different value in this two packages : pkg_std, pkg_a. And I would like to select the good one...
View ArticleSystemVerilog connecting a channel
I'm trying to hook up a new channel (channel 2) to an existing one (channel1) like so:channel channel1;channel channel2;extern function new(channel_type channel2);function subenv1::new(channel...
View ArticleRnadomize a variable inside a function
Hi, I want to randomize a variable defined in a function. The function is inside a package. I tried declaring a class inside the package and taking the instance of that class in the function. But...
View ArticleUsing $past in procedural code
Hi everyone, I'm not sure if this is the right place to post this. I have question regarding the usage of $past(...) and the other members of that family inside procedural code. The SV 2012 standard...
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