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Randomization in an initial block

I have a module defined as follows... module dut();    int i;    initial begin       i = $urandom_range(0, 500);       $display("The value of i is %1d", i);    end endmodule // dut I'm trying to...

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how to drive a clocking block output asynchronously

Our uvm_driver derivatives push values into the RTL via clocking blocks in interfaces.  This updates the signals synchronously as we typically want, but is there a recommended way to add an...

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assert(std::randomize(variable)) when assertions are turned off

What systemverilog standard defines when we use assert(std::randomize(variable)) when assertions are turned off   I am using it but bit confuse what should simulators do ? will it still randomize...

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Accessing Memory model from various sequences

I need to use a common memory for 2 sequences. I have a memory defined as uvm_component and all the logic needed to build a memory and its parameterizable. This memory is placed in the sequencer so...

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Running testcase in Questasim

Hi all,     I tried to run a testcase ( test_write_sequence) using command line in Questasim...  I had coded a AHB UVC and wanna to perform a simple write transaction..  But the tool called $finish in...

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run time issue questa sim

I ran a testcase using questa sim,i am getting following output.     ** Error: (vsim-3601) Iteration limit reached at time 0 ps     testcase run phase look like this. it printed info messages from...

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how to Constraint dynamic array

hi,    I will be ready to build one layer protocol testbench,  top level sequence item is transmit to lower level sequencer with large payload of data packet. assuption that         1)  trans_item  is...

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how to access verilog module internal signals in UVM testbench

i want to use my verilog module internal signal into UVM monitor and driver,how i should do that

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Program block: doesn't need to be instantiated? $finish called after all...

I am sharing something I stumbled on and learned from and also a question.   Question) It seems I don't need to instantiate a program block for its initial statement/s to run.  If I just add it to the...

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Asynchronous driving/monitoring in a SV-UVM framework

I have designed a SV-UVM framework initially for system simulation (for architecture evaluations). I have been using clocking blocks and genereated synchronous inputs (and monitoring) and as far as I...

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multiple SystemC tops in UVM_ML

Hello, Can I do this?       tops[0] = "SC:top1_sc";     tops[1] = "SC:top2_sc";     tops[2] = "SV:dut";                uvm_ml_run_test(tops, "");   Thanks

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Exiting simulation after some delay when errors exceed max_quit_count

Hi,   just wondering if there is a way to delay the quitting of simulation when max_quit_count number of errors occur. For e.g. :      >uvm_report_server svr;      >virtual function void...

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Help Required for Scoreboard Code

Rsepected All,   I found that there are many senior & well rich (by knowledge) engineers/ scientists exist over here in this forum. So I thought to take a chance to share my doubt in area of UVM...

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ISSUE with 11.4.14 Streaming operators (pack/unpack) if the size of source...

Hello All, module top; initial begin bit data_source []; byte unsigned pack_data[]; data_source = new[3]; pack_data = new[2]; for(int i = 0 ; i < (data_source.size()) ; i++)begin if ((i %2) ==...

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sequence DUT synchronization

I am trying to synchronize when sequences are sent to the DUT.  I send one transaction to the DUT at the beginning, and then I need to wait for the DUT to send out a transaction (much later) before I...

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type_id not in scope when deriving an uvm_object

Hello,   The learning curve of UVM is pretty steep... Maybe you can help me climb a little bit faster... ;-)   I have a working environment instantiating an agent. Now, I am trying to add a...

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Should UVM Analysis Interface write const objects

The current write method sends a handle to a non-const object. This allows any subscriber to a uvm_analysis_port to modify the object in the monitor. This is BAD.   To prevent this it would be ideal to...

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proper layering in an ethernet transaction class

I am creating an "Ethernet packet" class, extended from uvm_seq_item.  My first implementation was to include of course the Ethernet header, and then a polymorphic base class which holds all the data...

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Unable to link UVMC Lib?

Hi, I am trying to connect SV-SC ports via UVMC and while sccom -link I am getting below error. I am running simulation in windows. Using UVM-1.0p and UVMC-2.2. Individual compilation of SV and SC is...

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Possible contradiction in SV standard

I was just reading the 1800-2012 standard and I've come across something that strikes me as a possible contradiction. In section 18.8 Disabling random variables with rand_mode() it states that   The...

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