Handling protocol extensions
Hi everyone, I'm curious how you handle extensions to a protocol UVC. Let's say we have an APB UVC that implements the AMBA protocol. Let's also say that we have a DUT that, aside from the signals...
View ArticleSystemVerilog connecting a channel
I'm trying to hook up a new channel (channel 2) to an existing one (channel1) like so:channel channel1;channel channel2;extern function new(channel_type channel2);function subenv1::new(channel...
View ArticleRnadomize a variable inside a function
Hi, I want to randomize a variable defined in a function. The function is inside a package. I tried declaring a class inside the package and taking the instance of that class in the function. But...
View ArticleUsing $past in procedural code
Hi everyone, I'm not sure if this is the right place to post this. I have question regarding the usage of $past(...) and the other members of that family inside procedural code. The SV 2012 standard...
View ArticleRandomization in an initial block
I have a module defined as follows... module dut(); int i; initial begin i = $urandom_range(0, 500); $display("The value of i is %1d", i); end endmodule // dut I'm trying to...
View Articlehow to drive a clocking block output asynchronously
Our uvm_driver derivatives push values into the RTL via clocking blocks in interfaces. This updates the signals synchronously as we typically want, but is there a recommended way to add an...
View Articleassert(std::randomize(variable)) when assertions are turned off
What systemverilog standard defines when we use assert(std::randomize(variable)) when assertions are turned off I am using it but bit confuse what should simulators do ? will it still randomize...
View ArticleAccessing Memory model from various sequences
I need to use a common memory for 2 sequences. I have a memory defined as uvm_component and all the logic needed to build a memory and its parameterizable. This memory is placed in the sequencer so...
View ArticleDifference between RAL and RGM?
Hi, I have a doubt related to UVM 's RAL with compared to OVM's RGM. The OVM's RGM seems to have only two sets of registers i.e., the actual ones belonging to DUT and the other belonging to the...
View ArticleRunning testcase in Questasim
Hi all, I tried to run a testcase ( test_write_sequence) using command line in Questasim... I had coded a AHB UVC and wanna to perform a simple write transaction.. But the tool called $finish in...
View Articlerun time issue questa sim
I ran a testcase using questa sim,i am getting following output. ** Error: (vsim-3601) Iteration limit reached at time 0 ps testcase run phase look like this. it printed info messages from...
View Articlehow to Constraint dynamic array
hi, I will be ready to build one layer protocol testbench, top level sequence item is transmit to lower level sequencer with large payload of data packet. assuption that 1) trans_item is...
View ArticlePassing Transaction from Callback
Hi, I have a transaction in the callback and want to pass it on to the scoreboard. Since the callback are not uvm_components it is not possible to use the analysis ports. Thanks, Kans
View ArticleType parametrization of uvm_analysis_imp
I have a sequencer: class l3_ack_sequencer #(type REQ = uvm_sequence_item) extends uvm_sequencer #(REQ); `uvm_component_utils_begin(l3_ack_sequencer#(REQ)) `uvm_component_utils_end uvm_analysis_imp...
View Articlehow to pass value to a variable that is a derivation of uvm_object and not...
Hi, problem statement: I wanted to set a value to a variable that is derived of a uvm_object. I wanted to use the get/.set method prvious code snippet: function new(int len = 0) if(len > 0)...
View ArticleUVM_REG : override some addresses of old register model with another register...
Hi , I have a top register model. in that some address part is defined as memory. ( ex :- 0x0,4,8 ,c registers address then 0x10 memory then 0x20,0x24,0x28 ... registers) I have another register...
View ArticleGeneric Payload Vs PROTOCOL specific packets/seq_items in UVM env
Hello All, I am wondering for the use of generic payload instead of PROTOCOL specific packets/seq_items in UVM agents. Why : 1. This will help to verify the SC-TLM models(used as golden ref...
View ArticleHow to using package rightly in UVM?
Hi! often,in uvm test, host controller write or read registers through addresses,so, I define some parameter in a package using `define in replace of register address. then , import the package...
View Articlecan we use callback in other class than driver class or monitor or scorboard
1.can we use callback in other class than driver class or monitor or scorboard 2. in which class or module we can delete the callback
View Articleextending uvm_cmdline_processor - problem
I am trying to extend uvm_cmdline_processor as follows, but my extended version, ivm_cmdline_processor is not working. It seems like the *ref values* might not be getting passed correctly. There is...
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