run time issue questa sim
I ran a testcase using questa sim,i am getting following output. ** Error: (vsim-3601) Iteration limit reached at time 0 ps testcase run phase look like this. it printed info messages from...
View Articlehow to Constraint dynamic array
hi, I will be ready to build one layer protocol testbench, top level sequence item is transmit to lower level sequencer with large payload of data packet. assuption that 1) trans_item is...
View ArticleHow to using package rightly in UVM?
Hi! often,in uvm test, host controller write or read registers through addresses,so, I define some parameter in a package using `define in replace of register address. then , import the package...
View Article"Mixin" classes - parametrizing the base class
Hi UVM and SystemVerilog users, I've stumbled upon a particular pattern of writing a "utility" class, which I have called "mixin". class derived_class#(type BASE=base_class) extends BASE; .......
View ArticleSystemVerilog and pthreads
Hi champs, I have a specific use-case where i would like to drive signals into the test-bench, but they are coming from different pthreads. I see that my implementation works. My deeper question is,...
View ArticleShould uvm_hdl_force_time be declared automatic?
Hello, it's the first time I post in UVM forums, and I hope I have chosen the right way to highlight a possible problem in UVM (up to 1.2, as far as I know). The issue is that: task...
View Article'run' phase is ready to proceed to the 'extract' phase
I am trying to run a couple of test cases using script.But I am getting an error message after running the first test case.This stops the simulation.I am attaching the LOG with this mail.I don't...
View ArticleProblems creating objects in the "new" phase of a cofig object
My env configuration object consists of a bunch of other configuration objects. They all extend from uvm_object. When I try to create the smaller config objects inside the new function of the env...
View ArticleHow to dump data into a file in UVM
Hi, I would like to dump the output data into a file. I'm currently implementing it in the following way. integer mcd = $fopen("abc.txt", "w"); $fwrite(mcd, "This is my data"); $fclose(mcd); I...
View ArticleGet verbosity from a module
How can I get the current verbosity from within a module? I am trying to do something like this but the module can't find the function that returns the verbosity level. initial begin int...
View ArticleCodingStyle: handle name vs create's string name. To match or not?
CodingStyle: handle name vs create's string name. To match or not to match? What pros, cons, or team rules can you share about whether the string name passed into create should match the handle?...
View Article`uvm_*_utils macros useful in virtual class extended from uvm_object?
Does an abstract class (virtual class ....), which extends from uvm_object, benefit from using uvm utility macros (`uvm_component_utils, `uvm_object_utils)? As I understand, `uvm_component_utils and...
View Articleuvm sequence
Which is best method to start , randomize and end the sequence among the `uvm_do, start_item, `uvm_create, `uvm_send and the others and why? Please explain.
View ArticlePackage in SystemVerilog
Hi All, I have to access the associative array declared in top module from one of the TB files. All TB files are part of the package which is imported in the top module. When i am trying to access...
View ArticleDifferent packet types with single sequencer.?
Hi, Here I am attaching a sample code for my doubt: 1) class base_pkt extends uvm_sequence_items; - - endclass 2) class base1_pkt extends base_pkt; - - endclass...
View Articlefunctional coverage for AXI4 WREADY signal
For AXI write transaction axi wready signal determines whether the slave can accept the data. For write burst performance i need to capture the latency between "WREADY" and "next WREADY" signal. For...
View ArticleFactory override(set_type_override_by_type, set_inst_override_by_type)
Hi All, For set_type_override_by_type and set_inst_override_by_type, I am seeing same definition in uvm user guide as given below. set_type_override_by_type : A convenience function for...
View Articleuvm_config_db/uvm_resource_db
Hi All, Could anyone please let me know why resource is stored in two type of queue in uvm_config_db, The first kind of queues store the handles to the uvm_resource objects that have the common...
View Articleexecution region of UVM TB
Hi All, Simple systemverilog TB execute in re-active region because of program block, But in what region UVM tb executes as we do not use program block in UVM TB ? Thanks, Rahul Kumar
View ArticlePhases in uvm
Hi All, we use signature for build phase " build_phase(uvm_phase phase)", What is the use of "uvm_phase phase" in build_phase calling. Thanks, Rahul Kumar
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