hi,
I will be ready to build one layer protocol testbench, top level sequence item is transmit to lower level sequencer with large payload of data packet. assuption that
1) trans_item is toper level sequence item(transaction layer item)；
2) link_item is lower level sequence item(ie,link layer item)；
patial code as follows:
class trans_item extends uvm_sequence_item;
rand bit [31:0] mess_data[];
rand bit [15:0] mess_len;
constraint C_mess{
soft mess_data.size()==mess_len;
solve mess_len before mess_data;
}
................
class link_item extends uvm_sequence_item;
rand bit [31:0] mess_data[];
rand bit [15:0] mess_len;
constraint C_mess{
soft mess_data.size()==mess_len;
solve mess_len before mess_data;
}
................
class top_sequence extends uvm_sequence #（trans_item）;
rand bit [31:0] trans_data[];
rand bit [15:0] trans_len ;
constraint C_len{
trans_len==40;
trans_data.size()==trans_len;
solve trans_len before trans_data;
}
....
virtual task body()
`uvm_do_with(req,{req.mess_len==local::trans_len;
........................
foreach(local::trans_data[i])
req.mess_data[i]==local::trans_data[i];})
req.print();
endtask
endclass
class trans_to_link_seq extends uvm_sequence #(link_item);
uvm_sequencer trans_sequencer;
trans_item trans_req;
link_item link_req;
......
virtual task body();
trans_sequencer.get_next_item(trans_req);
trans_req.print()
// why can't print mess_data
........
`uvm_do_with(link_req,{link_req.mess_len==trans_req.mess_len;
..................
foreach(trans_req.mess_data[i]) link_req.mess_data[i]==trans_req.mess_len;})
.............
endclass
next, supposing that trans_sequencer has connected to link_sequencer by uvm_seq_item_pull_port ,seq_item_export
then , In test start top_sequence and trans_to_link_seq in fork jion statement;
class trans_test extends uvm_test;
virtual task main_phase (uvm_phase phase);
phase.raise_objection(this,"");
fork
top_sequence.start(env.agent.trans_sequencer);
trans_to_link_seq.start(env.agent.link_sequencer);
join_any
During the simulation,printing mess_len is not 40, questasim10.2c simulator has not reported assertion failed,in practual constraint is failed,
why can't print mess_data?
how dynamic array and x_len is constrainted?
how to send large payload of data packet to lower sequence or lower driver?
