ncvlog: *E,EXPENC - Expecting the keyword 'endclass'.
In my earlier UVM days I ran into this confusing error message a number of times. I just hit it again, so am posting my solution here, to share and to help myself rediscover when it is time. Error...
View ArticlePassing information between sequence and test
Hello, I have recently started using UVM with System Verilog. I need your help to resolve one of the problems I am facing. My test starts a sequence on a sequencer. In the sequence I am randomizing...
View ArticleCalling a task in the Agent from my test hangs the test in UVM
Hello, From my test I am calling a task defined in the Agent (env.agent.task_name). However the test is hanging as the task is not returning the control back to the test. I have added uvm_message...
View ArticleTLM transaction w/o a transaction type? (or w/ simple transaction type, like...
We are using TLM to pass transactions from SystemVerilog to SystemC. I have two cases where I am stuck. Actually, it is the same case, but I have two angles to my question. 1) Is it possible to...
View Articledefault input values for interfaces (for no-connects). to avoid warnings
May a module or interface have default 'no-connect' port connections, for ports that we don't need to connect? I need to use an interface which is shared between testbenches. I instantiate it a lot...
View ArticlePassing bit width parameters from top module to sequence item classes
There are a number of bit width parameters declared in the my top module. These parameters are passed to the DUT instance and parameterized interface instances. How can I also pass these parameter...
View ArticleSystemVerilog DPI
Can SystemVerilog "dynamic array" and "C point" be transfered through DPI? Thanks.
View ArticleAnalysis port that in dynamic array
Hi guys, I need to create a dynamic array for the analysis port in scoreboard, the reason I use dynamic array is multiple identical instances are created during run time. The implementation of the...
View Articleset register model to several agent
Hi, I am running into a situation which I have one register model, but there will be multiple identical agent need to use this regmodel to send sequence. assume I have: reg_agent agent[5]; and...
View Articlesimple override example - with error
I am trying to recreate/understand a testbench problem I currently have by creating a small example. In creating that small example, I am running into a problem. Below, in the "try1" and "try2"...
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Resetting a randc permutation sequence
Resetting a randc permutation sequence (See attached page from 1800-2012 SystemVerilog spec.) function bit [16:0] get_reasonable_buggy_data(bit [(A_SIZE-1):0] rid); string where="buggy"; // randc...
View ArticleRuntime Fatal Error : p_sequencer can't be casting from a parameterized...
Hi, Dear All, I have a very interesting problem here, image a multiple lanes (changeable) communication system, since some relationship maybe exist across those lanes, in order to model it, I just...
View ArticleInquiry in UVM
SA... the following lines are extracted from UVM user manual : class get_consumer extends uvm_component; uvm_blocking_get_port #(simple_trans) get_port; // the first line is understood to be...
View ArticleUVM sequence library
Hi all, I would like to give the test writer the a way to select sequence distribution from a sequence list. I'm using the uvm_sequence_library class in order to control the sequences selection in a...
View ArticleProcessor Verification
hello, * what to verify in Processor RTL, I'm working on SPARC V8, using UVM? what kind of assertions do we add. what are the general Processor specs? * If possible please provide or suggest some...
View Articlewait for 'delay' cycles
a simple question on wait, in driver run task, want to wait for item.delay clock cycles before moving on, may I know below ways are both good, repeat(<item>.delay) @ (posedge clk) assert...
View ArticleInterface Modport and bind: How to get them working
Hi In System Verilog the recommended approach to create interfaces is through modport suppose I have an interface like interface axi_if(input clk, input rst); logic arlen; clocking...
View Articlerandomize a string ?
Is it possible to randomize a string without home-brewing a function to do it? Can only integral data types be randomized, hence not strings? How much memory is allocated when a string is...
View ArticleVPI fault
HI, I have to verify 16 ahb slave. I am in dilemma whether to use single VIP slave agents or 16 slave agents , As my knowledge is concern we, at a time talk to only one ahb slave so i configure all 16...
View ArticleProgram blocks
What is the meaning of following "module (design) can not call task/function inside a program block. But a program can call task/function inside module (design)" Please explain it!! Thanks
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