Hello,
I have recently started using UVM with System Verilog. I need your help to resolve one of the problems I am facing.
My test starts a sequence on a sequencer. In the sequence I am randomizing the address (among other variables).
I want to pass the address that has been generated back to the test that started the sequence.
The test will use this address value to call execute a task in another agent.
I am not sure how do I pass this address back to the test from the sequence.
I don't want to hard-code the address. I thought of using the set_config_int() call in the sequence and doing a get_config_int() call in the test but that won't work as both will be executed in the "Run" phase and so can't determine whether the set_config will be called before the get_config.
Thanks.