Quantcast
Channel: UVM SystemVerilog Discussions Forum RSS Feed
Viewing all articles
Browse latest Browse all 410

Inquiry in UVM

$
0
0

SA...

 

the following lines are extracted from UVM user manual :

 

class get_consumer extends uvm_component;
uvm_blocking_get_port #(simple_trans) get_port;
 
// the first line is understood to be class declaration as extension from uvm_component class.
 
// I can't understand the 2nd line ,, could anyone here help me ?

Viewing all articles
Browse latest Browse all 410

Latest Images

Trending Articles



Latest Images