We are using TLM to pass transactions from SystemVerilog to SystemC.
I have two cases where I am stuck. Actually, it is the same case, but I have two angles to my question.
1) Is it possible to still use a TLM setup, but without a transaction type. (I realize that this is contradictory to the acronym.) A c-model has a debug function which takes no input arguments. So, when the SV testbench runs into a problem, it can call this function in the SystemC/c-model. As all of our connections now are sc_port/sc_export, with TLM, I'd like to stick with that flow if possible, rather than adding DPIs/VPIs/(PLIs) or any other mechanism to communicate between languages. However, since the function has no input arguments, I don't need a transaction type. So, is there a way to do a TLM call without a transaction type? (I suppose I could just use another transaction type and ignore the data.)
2) Imagine the above c-model input function that takes no input arguments. Let's say now that the c-model function takes a single integer as its input. So, now I do have a transaction type, but a very simple one. It seems like overkill, but do I still need to define matching .h and .svh (that extends uvm_sequence_item) transcation types and the related do_pack, do_unpack, etc. routines? It seems like overkill. I suspect that I must, if I want to use TLM.
(Given that the answer to this question must be, yes, does anyone out there just use a generic grab-bag transaction type for cases like this?)
//my thought of passing a transaction which is just an int
in sv tb:
uvm_blocking_put_port #(int) sb_debug_call1_to_cmodel;
in sc c-model
public tlm::tlm_blocking_put_if<sc_int <32>> //or smthg like that
Any thoughts? I know I just need to refresh myself on DPIs, but answers to the above question are welcome.