SVA for fairness of Round-Robin Arbiter
Are are any standard or recommended ways of verifying the functionality of the round-robin arbiter and more specifically checking the fairness? I'm looking for something that is scalable with the...
View Articlevirtual sequencer exit main phase prematurely
hi all, my SPI test stuck and test sequence is hung on wait_for_grant(). I turned the verbosity to UVM_DEBUG and found out virtual sequencer and physical sequencer exit from main phase and...
View ArticleIssue with add_hdl_path (peeking two sub modules regsiters)
HI I have two sub modules called A and B within DUT and trying to get register information of both A and B in back door using peek method. I have single ral block which includes both A and B...
View ArticleUsing DPI-C sin function
Hi, I'm trying to use DPI-C to import sin function, but it doesn't work, as a workround i had used a sin approximative function which finally give a static value of 2.5 (the offset value) i think...
View Articlepredictor / TLM model paradigm
What we've done in the past is have "phantom models" that are highly coupled with the RTL state machine. E.g. The RTL got a command, and performed: Read 0x1, Read 0x2, Write 0x1, Write 0x2. our...
View ArticleUse of intersection in cross coverpoints
I was under the assumption that once bins are created, the coverage would be collected only for those bins and the remaining combinations would be ignored. However, I noticed this was not the case when...
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Help regarding fork_join usage
Hi , Please help me the following code, module fork_join_any_process(); int me[3]; task automatic print_value; input [7:0] value; input [7:0] delay; begin $display("Waiting Passed value %d",value);...
View ArticleGenerating constrained random pre-load file for SoC TB
Hi All, Any idea how to use UVM to generate a pre-load files using constrained random method for SoC verification. Is it OK to have an UVM agent for this purpose which does not require any...
View Articleread register from RAL
Hi, I have a question refer to strange messages created by RAL read command. When the register is read, I receive a message like: uvm_pkg::uvm_parent_child_link l103=config_dmaw_seq r107=transfer...
View Articlereal port mappping
Hi all, i'm tryin to make a SV code with the following bloks: -Gaussian nois generator: the output is 16 bit, but i had converted it to real ( i had just putted real in place of STD_logic) -Low pass...
View Articleconfig_db usage: base class versus derived class objects
Is it possible to do a uvm_config_db::set() for an object of derived class type using the base class handle and later do a uvm_config_db::get() of same object using the derived class handle...
View ArticleIs it possible to have two implementation of b_transport?
I need to have two uvm_tlm_target_socket in a class and I need to do different set of things with the data received via two sockets. I was thinking if it is possible to have two implementation of...
View Articlenon-uvm message compliant, grep during report pahse.
is there way to search for the non-uvm compliant error message such as "ERROR - CSI Rx BFM " during the uvm report pahse of uvm environment? if we see this string error count variable need to be...
View ArticleUnique array elements without rand or randc
I have a variable logic [31:0] id which is not declared as rand or randc. I need different id's each time into an array logic [31:0] id_array [16].logic [31:0] id;logic [31:0] id_array...
View ArticleTurn off `uvm_info messages
Is there any way to turn off `uvm_info messages being displayed on the log while retaining `uvm_error and `uvm_fatal messages
View ArticleCommunication between uvm_sequence and uvm_component
I have two classes, one is block_seq which extends from uvm_sequence and other is block_cfg_mngr which extends from uvm_component. How do I exchange information between these two. I need to generate...
View ArticleRAL mapping reg_field to another reg_field
Hey! I'm think need some help with RAL. I have 2 registers and in reg A field F1(RO) mapped from reg B field F1(RW) how i must implement this using RAL?
View Articlewaiting for next clk edge, interfaces and clocking blocks
Q1) I'd like confirmation that the following waits for a posedge of clk are identical. (The code it refers to is far below.) 1) @(posedge my_play_if.clock); or @(posedge clk); 2)...
View ArticleImproving transaction recording
I am trying to improve transaction recording. So far we have used field automation macros, but to make debugging efficient I am trying to customize the recording. I've understood that the do_record...
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block level verification in a system setting
Let's say I have the following DUT. The UVM environment contains a chain of models/predictors. Input data flows down this chain and generates the expected CHIP output, which is compared to actual....
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