Test for suspend/resume operation of a flash memory
Hi everyone Let me ask a question on how to verify for program/erase suspend and resume operation of a flash memory design? How can I build a master monitor and scoreboard to check for that? Thanks Nhat
View Article[RAL] Dealing with 64b/32b register write/read with same reg_model
Hi, I have a single reg_model file generated from ralgen, Now there are some registers that can be written only using 64b write and some that can be written only using 32b write. What is the best way...
View ArticlePassing data in uvm_events.
I am trying to pass a trigger-specific information to my testbench. My triggers work correctly, but I am unable to get data using wait_trigger_data. I extended "event_object" from UVM_OBJECT, but...
View ArticleCould the interface be the type of another parameterized interface class?
The code is : interface block_if_wrapper #(type T=j_interface) (input clk, input rst_n); T j_if(clk, rst_n); endinterface Then there will be an syntax error, but I read the section of 8.25...
View ArticleRandomization of dynamic arrays
While randomizing a dynamic array we constrain the size of the array somewhat like this: rand byte data[]; constraint size_c { data.size() == 1000; } My question is regarding creation of dynamic...
View Articleoverlapped implication vs logical AND. |-> vs. &&
When used in a coverpoint, what is the difference between overlapped implication and logical AND? |-> vs. && cp_test : cover property ( @(posedge clk) disable iff (!resetn) A...
View ArticleIndex Pool Mgmt
Does UVM Provide any handy class similar to uvm_mem_mam to manage a pool of device indices (any numbers). To be more clear: Lets say I want to randomly pick an unused Device ID, I want to know if...
View ArticleOutput `uvm_info to file
Hi! I need redirect all uvm_info messages to some log file. My testbench contain dut module, some environment modules and classes, which using for monitoring and driving. In environment modules,...
View Articlewalk thru an enumeration
I needed to step thru an enum in a testbench today. As it took me a while to figure out how to do it, I post a small example here. I want to do it without making any assumptions of the values of the...
View Articlerandomize(argument) checks all constraints in scope
Yesterday, I learned that when randomize is called, all active constraints in the scope must be met ... even if you are passing a specific member as an argument to the randomize call. i.e. If you...
View Articleassertion to check for an array of channels
Consider the following code and the assertion to check for unknown data. If the code will change so that there will now be an array of valids and datas, what is the best way to change the assertion,...
View ArticleCoverage across multiple interfaces
I need to implement coverage across multiple interfaces. For example in the arbitor designs, it is of interest to see if multiple requests from different agents are driven at the same time. All the...
View ArticleWhen should we use uvm export
uvm_put_port is connected with uvm_put_imp. uvm_put_port will call put method which will be implemented in uvm_put_imp. My question is in which situation we use uvm_put_export
View ArticleHierarchical UVM Register Model and maps
Hi, I have a bus system with one master and upto 64 slaves. Each of the slaves has a register block, which is accessible by the bus master and a local SPI interface like this: +-----------+...
View ArticleAny DPI which can call Python in verilog testbench?
Hi, I am new to Python and I have been asked to build a UVM testbench which can call Python functions. Is there any way that I can do which is similar to DPI-C for C functions in verilog testbench?...
View ArticleIn-line random variable control
This section of the LRM is vague. 18.11 In-line random variable control What is the expected behavior for the following code? class child; rand int a; rand int b; constraint cb { a inside {[0:100]};...
View ArticleIs clock information allow in C with UVM testbench using DPI?
Is clock(signal from rtl or from testbench) allow to be used in C program to trigger event or delay?
View ArticleDelay in UVM driver
Hi all, I'm new with UVM and I came across a problem. I am working on an AXI RD VIP using UVM and I have the following issue. In the data_phase (the data channel driving) from the MASTER driver, I...
View ArticleUVM Phases: end_of_elobration
I referred couple of documents; cookbook, uvm 1.2 user guide, to know why end_of_elobration is required. However, i could not find answers for 'why it is required' and more specifically 'Is it...
View Articlerandomize() with inside syntax
How can I use "randomize() with" along with "inside", on the same line? Below is some code that solves the problem using >= and <=, but I'd like to use "inside". module top; class aclass;...
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