How to using package rightly in UVM?

Hi!

often,in uvm test, host controller write or read registers through  addresses,so, I define some parameter in a package using `define in replace of register address.

   then , import the package into my test lib package,

compile in order , test lib package is compiled lastly,

but when compling code ,report macro address can't find?

How to using package rightly in UVM?

Large projects may have many packages with complex interdependencies,How to using it rightly ?

thanks.

/wszhong