about uvm_reg::add_hdl_path_slice,can I assign a hdl varible declared as...
Hi, In rtl design, I have a wire [3:0] d signal. It's assigned with 4 signals declared as reg type. So my question is when I try to add hdl path slice for d what should I do? I tried to add each of the...
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uvm object into uvm sequence
Hi, I actually want to write a very simple sequence that use a variable of class extends uvm object type. So I firstly wrote a small class extends uvm object that contains all the properties I want...
View Articlehow to use uvm reg callback to implement reg_a read being qualified by a...
Hi, I have implemented a uvm reg block containing several uvm reg's. What I want to model is register reg_a has the following layout: {fld_a, fld_b,fld_c} and register reg_b has: {fld_st,fld_rsv} The...
View Articleiff usage (as a mechanism for waiting)
I happened across the following code. @(m_vif.smp_cb iff (m_vif.smp_cb.xyz_enable) ); To get to the crux of my question, let's consider it to be the below code. I don't think I've dropped anything...
View ArticleSC_FIXED and UVM ML Packer
Hi, I am trying to use SC_FIXED in a UVM ML environment, but the uvm_packer.h doesn't support sc_fixed. virtual uvm_packer& operator << (bool a); virtual uvm_packer& operator <<...
View ArticleHow to get virtual interface in sequence
HI Can any one provide some example for how to get virtual interface in sequence? I need to use the clk in sequece . Thanks praneeth
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View Article'run' phase is ready to proceed to the 'extract' phase
I am trying to run a couple of test cases using script.But I am getting an error message after running the first test case.This stops the simulation.I am attaching the LOG with this mail.I don't...
View ArticleProblems creating objects in the "new" phase of a cofig object
My env configuration object consists of a bunch of other configuration objects. They all extend from uvm_object. When I try to create the smaller config objects inside the new function of the env...
View ArticleHow to dump data into a file in UVM
Hi, I would like to dump the output data into a file. I'm currently implementing it in the following way. integer mcd = $fopen("abc.txt", "w"); $fwrite(mcd, "This is my data"); $fclose(mcd); I...
View ArticleGet verbosity from a module
How can I get the current verbosity from within a module? I am trying to do something like this but the module can't find the function that returns the verbosity level. initial begin int...
View ArticleCodingStyle: handle name vs create's string name. To match or not?
CodingStyle: handle name vs create's string name. To match or not to match? What pros, cons, or team rules can you share about whether the string name passed into create should match the handle?...
View Article`uvm_*_utils macros useful in virtual class extended from uvm_object?
Does an abstract class (virtual class ....), which extends from uvm_object, benefit from using uvm utility macros (`uvm_component_utils, `uvm_object_utils)? As I understand, `uvm_component_utils and...
View ArticleParameterized interfaces
a usual way to do it is to create a wrapper object and push the wrapper into config_db. Then get this wrapper object from config_db and assign it to the virtual interface pointer (not mentioning the...
View Articleuvm_resource_db usage
Hi, I am using uvm_resource_db to set and get any component configuration. But I am getting an error saying configuration object is not found. Its something that its not able to get the config object...
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