Is there a way to make the randomization of variables via randomize() use one of the different RNGs listed in 20.15 of the IEEE Std 1800 (such as $dist_normal or others)? Or does the use of one of the alternative RNGs require manually doing randomization via direct calls to those utility functions ($dist_normal, etc) in the post_ or pre_randomize() functions?
Greg
Hi,
In my current environment I have monitors class and parametrized scoreboard class. I am sending monitor transaction into scoreboard through the tlm analysis port. Below is snippet of code.
class pkt_monitor extends uvm_monitor
uvm_analysis_port #(pkt_item) pkt_collected_port;
function new(uvm_component parent = null)
pkt_collected_port = new("pkt_collected_port", this);
....
....
endclass
class pkt_sbd #(type T = uvm_transaction) extends uvm_component;
uvm_analysis_export #(T) sb_check_port;
// typedef pkt_sbd #(T) this_type;
function new(uvm_component parent = null)
sb_check_port = new("sb_check_port", this);
.....
.....
endclass
class top_env extends uvm_env;
pkt_sbd #(pkt_item) pkt_sbd_inst;
pkt_monitor pkt_monitor_inst;
build_phase()
pkt_monitor_inst = pkt_monitor::type_id::create("pkt_monitor_inst",this);
pkt_sbd_inst = pkt_sbd #(pkt_item) :: type_id::create("pkt_sbd_inst",this)
connect_phase()
pkt_monitor_inst.pkt_collected_port.connect(pkt_sbd_inst.sb_check_port)
endclass
While compiling above code there is a type incompatability issue observed
Error-[ICTTFC] Incompatible complex type usage
Incompatible complex type usage in task or function call.
The following expression is incompatible with the formal parameter of the
function. The type of the actual is 'class
uvm_pkg::uvm_analysis_export#(class pkt_pkg::pkt_item)', while the type of
the formal is 'class uvm_pkg::uvm_port_base#(class
uvm_pkg::uvm_tlm_if_base#(class pkt_pkg::pkt_item,class
pkt_pkg::pkt_item))'. Expression: this.pkt_sbd_inst.sb_check_port
Source info:
pkt_monitor_inst.pkt_collected_port.connect(pkt_sbd_inst.sb_check_port)
Any help is appreciated.
Hi ,
I would like to use some data items in one test: frame_packet, short_packet , illegal_packet.
In the uvm documentation i found that in order to switch between packets i should use factory setting in the test:
frame_packet::type_id::set_type_override(short_packet::get_type());
according to my understanding this completly replaces that data item and does not leave option to use frame_packet in this test.
Is there any other way to do it?
Thanks,
Ilan
I'm stuck on a problem I encountered with a use of the streaming operator to unpack into a dynamic array. Rather than write procedural code, I thought I could use it actually with some amount of success. Here is what the code more or less looks like:
uvm_pack_bitstream_t bit_vector;
bit bit_array[];
...
bit_vector = packer.get_packed_bits();
{<<{bit_array with [0 +: packer.count]}} = bit_vector;
myfunc(bit_array);
Yes, I'm trying to use "unadvertised" features of the UVM packer here. This has worked in many cases, but there is one case that led to the following:
# ** Fatal: Width do not match. Stream larger than variable.
I thought maybe the packer count was too large compared to the bits returned from the packer, but similar scenarios had executed previously in the simulation without error.
BTW, this is the only thing reported in the error, which is followed by the file and line number where it occurred (i.e. the streaming operator above).
So, any ideas or insight as to what is going on here?
TIA
Hello all,
Can I have 3 TLMs connected between a single sequencer and a single driver in UVM? In other words, I want 3 pipes/TLM connections to send three different kind of packets to the same driver from the same sequencer. Or in other words, can a sequencer has 3 exports? Can a diver has 3 ports, so that they can be connected with each other?
Please guide, thanks
Dear All,
Is it always the case that the TOP test class can control/manage the control knobs of sequences only? I mean, I want to override/control some parameters of driver class from top test class, can this be done? If yes, how can that be done? because top test class stimulates only a sequence, so how would the control knob of driver be controlled from top test class? any guidance will be helpfull.
Thanks
Is there any way to call python function from SystemVerilog?
Hello all,
Can there be more than one different kinds of sequences, containing different kinds of pkts, be nested in one single sequence? so that the test case scenerio, will be to show different kinds of pkts,going one after another in a single sequence to the driver? Please guide,thanks
Hi all,
I have 16 bit data line and in transaction class i declared as "rand".
But i want even even number's in one transaction and odd no number's in another transaction.
Please suggests me..
Regards,
Santhosh.
Dear All,
I need to send some high impedance/IDLE symbols (eg 101010...) between the two packets/frames for long time. So is it possible in UVM to send some random data (not through packets in the form of bytes)? If yes, how do I do it? Can this be done through some constraint variables, set in a config db object? Its urgent, so any guidance, regarding the process, will be appreciated.
Thanks
SPOILER ALERT: I figured this one out, but since I'd already typed up most of the question, here it is anyhow posted to the public domain. Comments welcome.
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Who can tell me how to pass a hex value into Systemverilog using uvm_cmdline_processor?
My current code is shown below as well as the command line option that is supplied.
bit [31:0] stimulus_xyz_min = 32'h12121212; // *** setting default here works fine
`uvm_info(get_type_name(), $psprintf("1st TEST-SETTINGS. xyz_min=%8h",stimulus_xyz_min), UVM_LOW)
if (cmdline_proc.get_arg_values(.match("+xyz_min="), .values(arg_values))) begin
stimulus_xyz_min = arg_values[$];
end
`uvm_info(get_type_name(), $psprintf("2nd TEST-SETTINGS. xyz_min=%8h",stimulus_xyz_min), UVM_LOW)
1st TEST-SETTINGS. xyz_min=12121212 2nd TEST-SETTINGS. xyz_min=30393039
+xyz_min=09090909 2nd TEST-SETTINGS. xyz_min=30393039
+xyz_min=00000000 2nd TEST-SETTINGS. xyz_min=30303030
+xyz_min=00000001 2nd TEST-SETTINGS. xyz_min=30303031
+xyz_min=00000002 2nd TEST-SETTINGS. xyz_min=30303032
+xyz_min=00000020 2nd TEST-SETTINGS. xyz_min=30303230
stimulus_lkj = arg_values[$].atoi();
and then in the sv spec found atohex.
`uvm_info(get_type_name(), $psprintf("1st TEST-SETTINGS. xyz_min=%8h",stimulus_xyz_min), UVM_LOW)
if (cmdline_proc.get_arg_values(.match("+xyz_min="), .values(arg_values))) begin
stimulus_xyz_min = arg_values[$].atohex();
end
`uvm_info(get_type_name(), $psprintf("2nd TEST-SETTINGS. xyz_min=%8h",stimulus_xyz_min), UVM_LOW)
+xyz_min=1ACECAFE 2nd TEST-SETTINGS. xyz_min=1acecafe
Hi,
I've created a UVM model for ethernet 10Gb MAC CoRE. There is a requirement to connect the AXI Bridge to my UVM model. I'm facing severe problems while integrating AXI Bridge to ethernet model.
Please provide some suggestions or share some document help for integration?
Thanks,
regards,
Mahee.
Q1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)?
Q2) In (the) UVM, do you think there is a place for checkers?
Context) We have VHDL rtl. For the data-interface between modules ABC and XYZ, we want to consolidate our protocol checking.
case1) ABC testbench. We now have the protocol checking in the sv interface which ABC and XYZ share
case2) XYZ testbench. the same
case3) Top level testbench (testing DUT which instantiates ABC and XYZ). Either we have to move the protocol checking to a module which is bind-ed to the VHDL. Or, we can bind the sv interface to the ABC-XYZ connection, to reuse the protocol checking of that interface.
Without using a macro or `include of the protocol checking code, I'd like to just have a package or some place where we store the protocol checking code and can reuse it, whether in an sv interface, or a module which we bind to the VHDL. Looking into this, and researching putting assertions into packages, I discovered checkers. Hence this line of questioning.
Please share your thoughts and experience.
Does the latest uvm no longer have `uvm_sequence_utils? In the user_guide, seems `uvm_object_utils(seq) is enough to associate a sequence with a sequencer? how does it work?
thanks,
//compare the name of the sequencer with the name that is given to the factory for the sequencer, when it is created