I am reading a register with using uvm_reg method read_reg.

so while doing this read transaction is happening on to the actual bus through agent  ,but the I am not getting read value in read_reg task in to a register sequence.

so I want to know what could be the issue for not getting read value on to the read_reg task.

Regards

sega 

Hi，experts,

I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error，but run time error appears. The code is as follows:
            1868 //pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}}; // change because of the run time error
            1869 if ((`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)) == 0) begin
            1870   pcie_item.first_be = {(length % `DW_BYTE_COUNT){1'b1}};
            1871 end     
            1872 else begin
            1873   pcie_item.first_be = {{(length % `DW_BYTE_COUNT){1'b1}}, {(`FDW_BE_WIDTH - (length % `DW_BYTE_COUNT)){1'b0}}};
            1874 end

`DW_BYTE_COUNT=4; `FDW_BE_WIDTH=4, length is one bit_stream type variable. line 1868 has been commented, changed to line 1869-1874. The reason why i change it is that there is such a run time error:
../sv/04_ref_model/ref_model.sv, line 1868: ** OTENF: S QOP_CONCAT (S,S) /* {} */
Note: OTENF is an internal error meaning Op_Table Entry Not Found
Assertion failed " Note: Set environment variable VCS_REPORT_ALL_OTENF to get all the OPTENF errors." at line 711 in file fun.c

An unexpected termination has occurred in /EDA_Tools/synopsys/vcs1209/linux/bin/vcs1

at ../sv/04_ref_model/ref_model.sv, 1730
During Codegen 
During Pass2 Module vcs_paramclassrepository Module vcs_paramclassrepository



--- Stack trace follows:
[Thread debugging using libthread_db enabled]
[New Thread 0xf7be9bb0 (LWP 24498)]
0xffffe405 in __kernel_vsyscall ()

Thread 2 (Thread 0xf7be9bb0 (LWP 24498)):
#0  0xffffe405 in __kernel_vsyscall ()
#1  0x00aebb26 in pthread_cond_wait@@GLIBC_2.3.2 () from /lib/tls/libpthread.so.0
#2  0x0aee7e64 in ?? ()
#3  0x00ae9371 in start_thread () from /lib/tls/libpthread.so.0
#4  0x00a41ffe in clone () from /lib/tls/libc.so.6
Backtrace stopped: Not enough registers or memory available to unwind further

Thread 1 (Thread 0xf7fd2700 (LWP 24497)):
#0  0xffffe405 in __kernel_vsyscall ()
#1  0x00a0447b in waitpid () from /lib/tls/libc.so.6
#2  0x009ae349 in do_system () from /lib/tls/libc.so.6
#3  0x009ae6c1 in system () from /lib/tls/libc.so.6
#4  0x00aef78d in system () from /lib/tls/libpthread.so.0
#5  0x0b3bc389 in tracker::StackAnnotator::getGdbOutput(char const*, char const*, char const*) ()
#6  0x0b3bd677 in tracker::StackAnnotator::dumpProcessStack(unsigned int, char const*, char const*) ()
#7  0x0b3b29c6 in dumpStackTrace ()
#8  0x0b3b74e7 in vcsAssertNoReturn ()
#9  0x08fbbf0d in ?? ()
#10 0x08fbc1c8 in BuildFUNsForRout ()
#11 0x0907ff8c in BuildMOPsForRout ()
#12 0x08f4e069 in ?? ()
#13 0x08f4f12e in ?? ()
#14 0x08f52423 in CodeGenC ()
#15 0x09187f31 in Phase234 ()
#16 0x08806fba in ?? ()
#17 0x088214ab in ?? ()
#18 0x088238ee in DoPass2 ()
#19 0x0876b5ab in doGAToPass2 ()
#20 0x0876be7a in c_main ()
#21 0x09293842 in main ()
Completed context dump phase location* 'Module' 'Module'
CPU time: 33.817 seconds to compile
make: *** [comp] Error 255

I have done the error analysis, my concept is that maybe the reason is that the value of `FDW_BE_WIDTH - (length % `DW_BYTE_COUNT) has the possibility of zero. So I add the judge condition about the value of `FDW_BE_WIDTH - (length % `DW_BYTE_COUNT), but it still reports the same error about line 1873. If I comment line 1873, the error disappears. It seems like that the problem has something to do with the action of compiler's analyzing the code.

Could any expert give me some information?

Thanks in advance.

Hello all,
Can A variable defined and used in one task, in one class, be used as it is in another class?But these two classes are completely independent of each other,in other words, they are not inherited from one another. So with this situation, can a variable defined in class Driver, be utilized in class monitor? For eg, I need to use a variable pkt_length (defined and used in driver class) in monitor class also so that I can use it in order to get the packets unpacked in monitor class.

Please help me with this querry. Thanks,

I am using UVM RAL (version 1.1c) and with my bus agent which supports pipelined requests and out of order responses. In RAL adapter I have set provides_responses=1.  Now when I have two read requests active in same sequence under fork-join. Now response can come in any order. I see that once the response comes for any read requests, RAL unblocks both the read requests. I looked into source code and I found that in uvm_reg_map::do_bus_read() API, while calling get_base_response(), it does not pass the "transaction_id" as an argument. So it takes default = -1 which mean it waits for response and if any response comes, it returns that does not seem right. As I have initiated both read requests from same sequence,there will be only one parent sequence(rw.parent) and responses for both read request will land in same "response_queue".  Now while picking the response from parent sequence "response_queue", we should have use the "transaction_id". 

I would like to know if I am making any mistake to understand the behavior or it is indeed an issue.

uvm_reg_map::do_bus_read() implementation:

======================================

   if (adapter.provides_responses) begin
        uvm_sequence_item bus_rsp;
        uvm_access_e op;
        // TODO: need to test for right trans type, if not put back in q
        rw.parent.get_base_response(bus_rsp);
        adapter.bus2reg(bus_rsp,rw_access);
      end
 

======================================

uvm_sequence_base::get_base_response task implementation:

==========================================

virtual task get_base_response(output uvm_sequence_item response, input int transaction_id = -1);

    int queue_size, i;

    if (response_queue.size() == 0)
      wait (response_queue.size() != 0);

    if (transaction_id == -1) begin
      response = response_queue.pop_front();
      return;
    end

    forever begin
      queue_size = response_queue.size();
      for (i = 0; i < queue_size; i++) begin
        if (response_queue[i].get_transaction_id() == transaction_id)
          begin
            $cast(response,response_queue[i]);
            response_queue.delete(i);
            return;
          end
      end
      wait (response_queue.size() != queue_size);
    end
  endtask

=====================================
 

Hello all,

I want to pass the output of one function (10b8b decoder) into the input of another function viz. drive, where in drive function, I am creating the array out of each byte received from decoder. But when I am trying to Return that value from decoder, its not happening.

Can someone please tell me how to return the decoder output value and take it in as an input into the drive function? I would appreciate it.

Thanks

In SystemVerilog we can have dynamic unpacked arrays and they can be passed to a function/task. I was wondering if there is a way to pass dynamic packed arrays to a function/task. For example consider the following code:

module test;
  logic [3:0] A;
  logic [7:0] B;

  task automatic double(ref [3:0] val);
    val = val * 2;
    $display("%b",val);
  endtask

  initial begin
    A = 3;
    double(A);
    B = 5; 
    //double(B); ** Error because of size mismatch
  end

endmodule

here the task can only have a 4-bit input argument so if B is passed an error occurs. I am interested to know if there is any way to pass packed arrays of different size to a task/function. In previous example if the arrays were unpacked I could use:

  task automatic double(ref val []);

but I have no idea what I should use for packed arrays. In VHDL having variable size input arguments is very easy. For example the same code can be written like this:

use std.textio.all;

entity test is
end entity;

architecture arch of test is

  procedure double(val: bit_vector) is
    variable temp : bit_vector(val'left downto val'right);
    variable l : line;
  begin
    temp := val sll 1;
    write(l,temp);
    writeline(output,l);
  end procedure;

begin

  process
    variable A : bit_vector(3 downto 0);
    variable B : bit_vector(7 downto 0);
  begin
    A := "0011";
    double(A);
    B := "00001111";
    double(B);
    wait;
  end process;
  
end architecture;

I appreciate any idea on this.

Thanks

Hi all,

I have one problem about variable part select of Verilog. If you know the width, but the upper or lower range is a variable, you can use variable part select.

eg : 

addr[idx_bits-:8] = {8{1'b1}}; 

t's okay.

But if you know the upper or lower range, the width is a variable, how can you do? I adapt the similar way of variable part select.

eg: 

addr[8-:idx_bits] = {idx_bits{1'b1}};

VCS reports such an error:

Hello all,

I am working on piso(parallel in serial out). I am receiving the 10bits byte properly upto foreach loop, But after that data is not being shifted properly in shift register and its not getting serialized. Following is the code for the piso task.

 
task piso(encodrout1); 
        bit[9:0]encodrout1[]; 
        $display("san355- Display of the bytes array received inside the PISO %p",encodrout1); //%h
                uvm_report_info(get_full_name(),"Received All 10bits into the PISO...",UVM_LOW); 
              
      uvm_report_info(get_full_name(),"Driving 10bits and converting into serial bitstream.....",UVM_NONE);
     
      foreach (encodrout1[k]) 
         begin
          // automatic 
          reg [9:0] load;
          //automatic bit [9:0] load; // =0;
           reg [4:0] counter_d = 0;
           
           dut_vi.reset <= 0; 
    
       load = encodrout1[k];
     
                         $display("san340- Display of the load %b",load); 
                         $display("san340- Display of the load %h",load); 
                    
     @(posedge dut_vi.clock) 
     
     //for (int i = 0; i < 10 ; i++) //I guess this line is not needed
     begin
                  // repeat(10)@(posedge dut_vi.clock)
                 // @(posedge dut_vi.clock) 
                   counter_d = counter_d + 1;    
                  
                   load[9:0] <= {load[8:1] & load[0]} ; //THIS LINE DOESNT WORK, GIVES ERROR: Error: driver72.sv(269): LHS in non-blocking assignment may not be an automatic variable
    
     load[9] = load[8];
                   $display("san370- Display of the load %b",load); 
                   // @(posedge dut_vi.clock)
                   dut_vi.data <= load[9];
             load[8] = load[7];
             $display("san371- Display of the load %b",load); 
             // @(posedge dut_vi.clock)
             dut_vi.data <= load[8];
                   load[7] = load[6];
                   $display("san372- Display of the load %b",load); 
                   // @(posedge dut_vi.clock)
                   dut_vi.data <= load[7];
             load[6] = load[5];
             $display("san373- Display of the load %b",load); 
             //  @(posedge dut_vi.clock)
             dut_vi.data <= load[6];
             load[5] = load[4];
             $display("san374- Display of the load %b",load); 
             //  @(posedge dut_vi.clock)
             dut_vi.data <= load[5];
             load[4] = load[3];
             $display("san375- Display of the load %b",load); 
            // @(posedge dut_vi.clock)
             dut_vi.data <= load[4];
             load[3] = load[2];
             $display("san376- Display of the load %b",load); 
            // @(posedge dut_vi.clock)
             dut_vi.data <= load[3];
             load[2] = load[1];
             $display("san377- Display of the load %b",load); 
            // @(posedge dut_vi.clock)
             dut_vi.data <= load[2];
             load[1] = load[0];
             $display("san378- Display of the load %b",load); 
            // @(posedge dut_vi.clock)
             dut_vi.data <= load[1];
                   load[0] = load[9]; 
                   $display("san379- Display of the load %b",load); // */                   
                   dut_vi.data <= load[0];
            
      // repeat(10)@(posedge dut_vi.clock)
       counter_d = counter_d + 1;
       $display("san365- Display of the counter_d %d",counter_d); //%h
       $display("san369- Display of the load %h",load); //%h
       $display("san369- Display of the load %b",load); //%h
     
               uvm_report_info(get_full_name(),"Display of load inside PISO2222.....",UVM_NONE);
     end  
     //ser_OUTPUT=load[9]; // this needs to be connected to the serial line of DUT It works here
     /*@(posedge dut_vi.clock) 
     dut_vi.data <= load[9]; //serial data goes out
     @(posedge dut_vi.clock) 
     dut_vi.data <= load[8];
     @(posedge dut_vi.clock) 
     dut_vi.data <= load[7]; //*/
     $display("san384- Display of the load[9] %b",load[9]); //%h
     //dut_vi.data <= ser_OUTPUT; //
     $display("san385- Display of the dut_vi.data %b",dut_vi.data); //%h It works here
     //end
         end
                    
       endtask : piso 
 

Any help will be appreciated, thanks

I am using uvm_pw_scoreboard package available on accelera Contributions.I have following queries about it .

1. Why does this package uses uvm_analysis_export and analysis_fifo implementation instead of uvm_analysis_imp in pw_checker_predictor as well as pw_scoreboard.

2. I want to pass unique id to each transaction, to do this i have implemented as below:

my_local_predictor.sv file(not extended from pw_checker_predictor)

uvm_analysis_port #(item) predict_port;

predict_port = new ("predict_port",this);

item.set_transaction_item(unique_id);

$display("Predictor unique_id =%d",unique_id);

predict_port.write(item)

In extended pw_scoreboard

function int get_stream_id(uvm_transaction t )

     $display("Scoreboard unique_id =%d",t.get_transaction());

     get_stream_id = t.get_transaction_id();

endfunction

Output:

Predictor unique_id = 2;

Scoreboard unique_id= -1;

Any help is appreciated.

When agents are configured, I typically see something like this:

uvm_config_db#(int)::set(this,"testbenchA.masterA_hostB.agentpink","is_active",UVM_ACTIVE);

Isn't UVM_ACTIVE of type bit?  I see it 'described' here in an enum and given a default value.

src/base/uvm_object_globals.svh: typedef enum bit { UVM_PASSIVE=0, UVM_ACTIVE=1 } uvm_active_passive_enum;

So shouldn't the uvm_config_db line not be:

 uvm_config_db#(int)::set(this,"testbenchA.masterA_hostB.agentpink","is_active",UVM_ACTIVE);

Hi ,

Is there any way to control the sequences distibution on UVM? 

For example when one would like to give higher probablily to some sequences over the other?

Can this be controlled from the test?

Thanks, 

Ilan

I was wondering about the need for the API call include_coverage(...) in uvm_reg.  It appears that build_coverage (...) would be sufficient to build whatever coverage is required in the current scope.

Is there a recommended  use model that clearly distinguishes the use of these 2 calls?

As the include_coverage() call contains a scope parameter,  I realize we can specify coverage models for any register object from some other scope... But where would one call this routine ?   For build_coverage it is clear that it applies to the current scope.

Thanks for your help

Loganath

I had expected all 3 of these calls to randomize to return values using the constraint.  However, the first does not.  Can anyone tell me why?

class thursday_seq extends junk_seq_seq;  //which extends uvm_sequence

   rand int count;
   constraint c1 { count >= 2; count <= 9; }

   function new(string name="thursday_seq");
      super.new(name);
      if (std::randomize(count)) begin 
         `uvm_info("",$psprintf(" cnt=%0d .....",count),UVM_LOW) end
      else $finish;
      if (randomize(count)) begin 
         `uvm_info("",$psprintf(" cnt=%0d .....",count),UVM_LOW) end
      else $finish;
      if (this.randomize()) begin 
         `uvm_info("",$psprintf(" cnt=%0d .....",count),UVM_LOW) end
      else $finish;
      $finish;
   endfunction:new

UVM_INFO @ 0: reporter@ []  cnt=415747889 .....
UVM_INFO @ 0: reporter@ []  cnt=9 .....
UVM_INFO @ 0: reporter@ []  cnt=2 .....

It seems what is happening is that while std::randomize and randomize are calling the same method in the standard package, the standard version is oblivious to local constraints.

I see in 1800-2012.pdf (SV spec), sec. 18.5.2 "The randomize() method is virtual and therefore honors constraints of the object on which it was called, ..." (highlighting mine)

Later in the spec, there is reference to the 'scope of the randomize('  which confuses me a bit, if the constraints are always to be honored.  (Although, I suppose in the first two cases above "of the object on which it was called" is not true, b/c I don't call it on the object, but on a property of the object.)  Is that correct?

After doing a bunch more reading, I am going to continue with this post for feedback.  Here is something more I learned.

This quote in section "18.12 Randomization of scope variables—std::randomize()" I think explains it all for me.

I'm a bit unsure, but I think the answer to my question is this.

"without the need to define a class" and "in the current scope", from above, imply that std::randomize performs only on the scope that is passed to it.   i.e. if I pass it a class object, then it knows of that object's constraints.    If I pass it a data-member of a class, then the scope that data-member exists in is not seen (i.e. any constraints which are in the scope above that data-member are not seen).  Though they could be replicated as inline constraints.).   

The local randomize knows of all the constraints in the object from which it is called.

Do I understand this correctly?  I think I just walked myself through understanding this.  Comments welcome.

thx,

note: using Cadence's IUS12.1-s004

Hi,

I'm trying to determine if "import" statements should be within package statements or not, when it comes to random stability.