Instance override of a parametrized type

July 16, 2013, 1:41 pm

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I'm attempting to do an instance override on a parametrized type in UVM, but I can't seem to set a correct path to the instance I want to override. The code below

factory.set_inst_override_by_type(typical_item#(1, 1)::get_type(), typical_item_1#(1, 1)::get_type(), override_path);

works if

override_path == "*"

which is matching everything and thus doing in essence a type override - not what I want. If I try to be more specific (even entering something like uvm_test_top) no instances are overridden.

Is there a way to find out the correct instance path to some sequence so I can use it in my override call?

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Best way to emulate destructors in SystemVerilog classes

July 23, 2013, 8:10 am

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SystemVerilog does not have destructors like C++, so it will automatically handle garbage collection and memory management for you, to a degree. I have a problem in which I would like to track a collection of objects, each with a unique ID. I defined a static queue to manage the list of IDs. A new ID is created and checked for uniqueness in the constructor. The problem is what is a good way to remove the ID from the queue when the object is destroyed, no longer needed. I could fudge it with something like requiring the client to make some sort of method call that "deallocates" the object before it goes away, but that seems kludgy to require the client to manage that.

Any ideas?

TIA

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UVM do_copy function

July 24, 2013, 8:53 pm

≫ Next: accessing a generate block hierarchy

≪ Previous: Best way to emulate destructors in SystemVerilog classes

Hello, i am new in UVM and Sv, i wanted to knw the UVM do_copy function in detail

1.the need of $cast(rhs,rhs_)

2.need to call super.do_copy.

plz explain in detail. Thank u

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accessing a generate block hierarchy

July 25, 2013, 12:53 am

≫ Next: How can I record a dynamic array of reals?

≪ Previous: UVM do_copy function

Hi all,
I'm trying to access a verilog hierarchy which was generated by a generate block - but I'm having some problems with it. for example:

verilog file: (let's assume it is located at "testbench" hierarchy, and an interface named "some_interface" is already defined)

genvar i;
generate
for (i=0;i<3;i++)
begin : GENERATE_HEADER
some_interface some_interface_inst(clk);
assign some_interface_inst.x=1'b0;
assign some_interface_inst.y=1'b1;

end

endgenerate

systemverilog file:

virtual some_interface some_interface_arr[0:2];

for (int i=0;i<3;i++)
some_interface_arr[i]=testbench.GENERATE_HEADER[i].some_interface_inst;

I believe I can't access a generated verilog hierarchy with a system-verilog for loop (variable i). Am I correct? and if so - is there a way to pass this obstacle?
Thanks in advance,
Eyal.
P.s - What I'm generally trying to do is to get handles to the instantiated interfaces (some_interface) and pass them to system verilog objects in my testbench, using the virtual interface array.

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How can I record a dynamic array of reals?

July 26, 2013, 10:47 am

≫ Next: How to import a VHDL constant in system verilog

≪ Previous: accessing a generate block hierarchy

I've read the UVM 1.1 references searching for this answer. In the `uvm_field_array_*macros session there's no `uvm_field_array_real.

Does anyone have the answer?

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How to import a VHDL constant in system verilog

July 31, 2013, 11:58 pm

≫ Next: uvm_scoreboard requires analysis import to compile. why?

≪ Previous: How can I record a dynamic array of reals?

Hi,

I want to use a value which is a constant in my VHDL design file. I want to make my env. generic depending on the value of this constant. How do i import this constant from VHDL to SV

Thanks,

Parag

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uvm_scoreboard requires analysis import to compile. why?

August 2, 2013, 1:09 pm

≫ Next: How to lock the sequencer from the driver

≪ Previous: How to import a VHDL constant in system verilog

Below I define a uvm_scoreboard. Why will this not compile when I remove the (3) lines THIS AND THAT? Should it?

`uvm_analysis_imp_decl(_rcvd_pkt)  //THIS
class dpx_rr_scoreboard extends uvm_scoreboard;

   `uvm_component_utils(dpx_rr_scoreboard)

   virtual function void write_rcvd_pkt(input some_trans t);  //AND THAT
   endfunction : write_rcvd_pkt                               //AND THAT

endclass : dpx_rr_scoreboard

I am using irun 12.X and get the following error when I remove the aforementioned lines:

class dpx_rr_scoreboard extends uvm_scoreboard;

ncvlog: *E,FAABP1 (/user/posedgeclk/tb/dpx_rr_scoreboard.svh,25|46): task, function, or assertion instance does not specify all required formal arguments [10.2.2][10\

.3(IEEE)].

I poked around in the uvm class library just a bit, but did not figure this out.

Any ideas? Is this a uvm thing or Cadence thing (trying to enforce that I write sensible code) or just fooling thing on my part?

I am asking Cadence directly as well, but wanted to throw this out to the crowd.

**I am just trying to get a shell of a scoreboard compiling, and don't care that it does nothing yet. Let's ignore the fact that I don't have uvm_analysis_imp_rcvd_pkt created.

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How to lock the sequencer from the driver

August 8, 2013, 6:57 am

≫ Next: Huge sv file - vcs out of memory

≪ Previous: uvm_scoreboard requires analysis import to compile. why?

I am trying to create a driver with two stage pipeline using the example given on uvm_transaction entry of uvm on-line reference as shown below.

task do_item();
forever begin
mbus_item req;
lock.get();
seq_item_port.get(req); // Completes the sequencer-driver handshake
accept_tr(req);
// request bus, wait for grant, etc.
begin_tr(req);
// execute address phase
// allows next transaction to begin address phase
lock.put();
// execute data phase
// (may trigger custom "data_phase" event here)
end_tr(req);
end
endtask: do_item

when I compiled my version using irun, it complained about

ncvlog: *E,ILLHIN (driver.sv,233|13): illegal location for a hierarchical name (in a package).

Could anyone please tell me what is the right way to lock the sequencer in the driver.

thanks,

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Huge sv file - vcs out of memory

August 10, 2013, 9:46 pm

≫ Next: SV assertion comparing multicycle data bus - specific question

≪ Previous: How to lock the sequencer from the driver

Hi all,

I've created a uvm sv file (it is actually a register block), which has the following format:

class X extends uvm_reg_block;

rand reg1 x1[255];

rand reg2 x2[255];

rand reg3 x3[255];

// and so on - thousands of registers (reg1,reg2,reg3 are rand classes).

constraint reg1_0_const {...};

constraint reg1_1_const {...};

constraint reg1_2_const {...};

...

constraint reg2_0_const {...};

constraint reg2_1_const {...};

constraint reg2_2_const {...};

...

constraint reg3_0_const {...};

constraint reg3_1_const {...};

constraint reg3_2_const {...};

...

endclass

Since I have a huge number of registers, and each register has several corresponding constraints (regarding each of its fields), the sum of the constraints is enormous (>50K). when I try running a test with the following configuration, I get a vcs error which states "vcs Error-[NONMEM] Out of memory" (after getting "starting vcs inline pass"). I tried running with a 64 bit flag, but the problem remains. when I clear the constraint code (the main "X" class remains, but the constraints logic is omitted) the problem vanishes.

Is there a way to avoid this issue?

I don't really know why the problem occurs :

1. Is it just since the class has too many lines of code in it? if so, maybe splitting it to smaller classes and instantiating them in a higher level class would help?

2. Will splitting the class into several hierarchies and using inheritance might solve the problem?

I'd appreciate any idea.

Thanks,

Eyal.

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SV assertion comparing multicycle data bus - specific question

August 14, 2013, 11:19 am

≫ Next: Don't care bit handling in UVM RAL

≪ Previous: Huge sv file - vcs out of memory

Assertion experts,

I know how to do a check of new_data_io (see below) in terms of 'regular' SV code, but will someone comment on how/if I can put this into a nice assertion to put into my interface?

All based on posedge clk:

valid_io    - indicates valid data 
data_io     - the data
new_data_io - signifies that data_io has changed since the previous valid_io cycle

So, when (valid_io && (!new_data_io)), the receiver can just use the most recently valid data.

(The fact that there can be cycles of !valid_io, while this assertion is active, is what's throwing me off. Well, and also the concept of retaining previous state of data_io. Perhaps this might not be suitable for an assertion and I should just stick with a small process to do the check.)

thx for any feedback,

Assertion Novice

(Why ever did I loan out my book Art of Verification with SystemVerilog Assertions by Faisal Haque?)

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Don't care bit handling in UVM RAL

August 20, 2013, 12:36 am

≫ Next: parsing using system verilog

≪ Previous: SV assertion comparing multicycle data bus - specific question

Not sure do you have similar problem? I have a problem in handling the reset value in RAL.

f the reset value of a field in the register is don't care, what can I do for it?

Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked.

Do you guys think it is a feasible way? Thanks.

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parsing using system verilog

September 2, 2013, 4:36 am

≫ Next: Signed field in RAL model

≪ Previous: Don't care bit handling in UVM RAL

Hi,

I have an IP with built in tests, written in pyhton.

I want to parse those tests and use them in higher level (uvm testbench). Eventually each test will be a uvm sequence.

For that I need a system verilog parser.

Is there a reference that I can use for this purpose?

example for lines in existing test:

WriteBlock SLAVE 0x0000ffff

Data 8

a5a5a5a5 ffffffff

Thanks

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Signed field in RAL model

September 10, 2013, 10:20 pm

≫ Next: uvm_do_with constrain problem with sequence

≪ Previous: parsing using system verilog

Hello All,

I have some queries regarding RAL model :

(1.) How to declare any particular Register's filed as "signed" in RAL model?

(2.) By default all the register fields in RAL model are "unsigned" or "signed"?

If possible please guide me for the same.

Thanks,

Bonny G. Vora

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uvm_do_with constrain problem with sequence

September 11, 2013, 11:33 pm

≫ Next: UVM_FATAL invokes $finish(1)

≪ Previous: Signed field in RAL model

class my_transaction extends uvm_sequence_item;

....

int a;

int b;

int c;

....

endclass

class my_sequence extends uvm_sequence#(..)

....

my_transaction tx;

...

`uvm_do_with(tx,{tx.a==1;tx.b==1;tx.c==1;})

....

endclass

class my_complex sequence extends uvm_sequence#(...)

my_sequence seq;

`uvm_do_with(seq,{seq.a==0;seq.b==0;seq.c==0;}) // This Doesn't work........How can I change value of a,b,c in this situation?

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UVM_FATAL invokes $finish(1)

September 12, 2013, 5:50 am

≫ Next: Scoreboarding the Register Model

≪ Previous: uvm_do_with constrain problem with sequence

To circumvent UVM calling on $finish directly when completing normally, one would override "finish_on_completion" to 0 before calling "run_test()". What I do is:

uvm_top.finish_on_completion = 0;

run_test();

$finish(2);

The last statement tells the tool to publish useful simulation statistics such as total run time, memory used, etc. This information is very useful in monitoring large batches of simulations for many purposes, among which is farm optimisation and debugging bad code consuming lots of memory.

However, when UVM_FATAL is invoked, effectively a $finish(1) is called - and the above-mentioned information is thrown away. Is there a way to overcome this and get UVM to call $finish(2) or at least allows this to be customised? Probably via a uvm_config_db::set() and uvm_config_db::get() ? Or perhaps I am not aware of something that already allows this?

A work-around would be avoid using UVM_FATAL and use UVM_ERROR with a following $finish(2) - but this is clumsy and widespread change is required.

Thanks

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Scoreboarding the Register Model

September 17, 2013, 10:55 am

≫ Next: Register "abc_rm.mem" value read from DUT (0x0000000000000002) does not match mirrored value (0x000000000000000X)

≪ Previous: UVM_FATAL invokes $finish(1)

I am attempting to implement the UVM register model in my testbenches. Are there reference implementations that connect to a scoreboard? Our methodology uses C++ reference models with fields identical to the registers in the DUT. I would like to receive an event from the register model with an access type, register name or address and data to pass to DPI functions for comparison. Are there any interfaces for this built in to the model already?

Thanks.

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Register "abc_rm.mem" value read from DUT (0x0000000000000002) does not match mirrored value (0x000000000000000X)

September 19, 2013, 7:09 am

≫ Next: connect uvm_analysis_export (SV) and tlm_aanalysis_port (SC) with UVMC

≪ Previous: Scoreboarding the Register Model

Can any one please explain what this would mean .

I can write on the this register perfectly .

The only problem is reading .

I am performing uvm_reg_single_bit_bash_seq on this register .

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connect uvm_analysis_export (SV) and tlm_aanalysis_port (SC) with UVMC

September 19, 2013, 7:26 am

≫ Next: how to (best) delay the start of built-in UVM register test stimulus

≪ Previous: Register "abc_rm.mem" value read from DUT (0x0000000000000002) does not match mirrored value (0x000000000000000X)

Hi,

I am trying to connect uvm_analysis_export (SV) and tlm_aanalysis_port (SC) using UVMC like the following:

uvm_analysis_export #(obs_xact#(WL,DEP)) sc_export;

uvmc_tlm#(obs_xact#(WL,DEP))::connect(sc_export,"fft_ap");

but I got the follow error message:

Incompatible complex type usage in task or function call.
The following expression is incompatible with the formal parameter of the
function. The type of the actual is 'class
uvm_pkg::uvm_analysis_export#(class test_pkg::obs_xact#(12,512))', while the
type of the formal is 'class uvm_pkg::uvm_port_base#(class
uvm_pkg::uvm_tlm_if#(class test_pkg::obs_xact#(12,512),enum
uvm_pkg::uvm_tlm_phase_e))'. Expression: this.sc_export
Source info:
uvmc_tlm#(test_pkg::obs_xact#(12,512),uvm_pkg::uvm_tlm_phase_e,uvmc_pkg::uvmc_default_converter#(uvm_pkg::uvm_object))::connect(this.sc_export,
"fft_ap", null ...

Isn't uvm_analysis_export is extended from uvm_port_base#(uvm_tlm_if#())?

Thanks

Sam

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how to (best) delay the start of built-in UVM register test stimulus

September 23, 2013, 7:20 pm

≫ Next: How inputs are driven in UVM ?

≪ Previous: connect uvm_analysis_export (SV) and tlm_aanalysis_port (SC) with UVMC

I've run into the following issue using the built-in UVM register tests.

The built-in UVM register tests (seem to) start R/W-ing immediately after top-level reset is released.

This was fine, initially. See attached image "Capture".

We now have some delay between the release of top-level reset and the actual reset going to the register block. This is resulting in a read occurring before reset to the rtl regblock is released, and causes the test to hang. See attached image "Capture2".

Without modifying the built-in register tests/sequences, how would anyone suggest that we cleanly delay the stimulus? Perhaps I just need to make the stimulus aware of the different reset when the model/stimulus is generated, or simple add some delay to a phase before the R/W-ing starts. (The former sounds right. If that's the solution, I'll need to figure out how we're generating the model/stimulus.)

I've just started hunting around for the built-in UVM register test sequences and will return to it tomorrow, but will anyone tip me off as to what names I should be searching for?

thanks

This has been useful, https://verificationacademy.com/cookbook/registers/builtinsequences, but it seems I need to do some more reading and hunting before I grasp how the built-in register stimulus is created and used.

Attached Thumbnails

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How inputs are driven in UVM ?

September 24, 2013, 7:43 am

≫ Next: ncvlog: *E,EXPENC - Expecting the keyword 'endclass'.

≪ Previous: how to (best) delay the start of built-in UVM register test stimulus

Hello,

I'm newbie to UVM. I'm trying to develop a 2:1 Mux using UVM standard classs libraries.

I've a question that how the inputs are generated using Sequences and driven at driver side to interface ?

-Thanks

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