Type parametrization of uvm_analysis_imp

I have a sequencer: 

class l3_ack_sequencer #(type REQ  = uvm_sequence_item) extends uvm_sequencer #(REQ);

    `uvm_component_utils_begin(l3_ack_sequencer#(REQ))
    `uvm_component_utils_end

    uvm_analysis_imp #(REQ, l3_ack_sequencer) generate_res;

    function new (string name, uvm_component parent);
        super.new(name, parent);
        generate_res = new("generate_ack", this);
    endfunction


    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);
    endfunction
    
    virtual function void connect_phase(uvm_phase phase);
        super.connect_phase(phase);
    endfunction

    // Generate ack
    virtual function void write(REQ item);
    endfunction   
endclass

Then I declare a handle somewhere:

l3_ack_sequencer  #(core_l3q_ireq_tran) l3r_ireq;

Using Synopsys VCS I have an error:

Can anyone help me to solve this problem or explain why it cant be solved?