Register read via register model.
I am reading a register with using uvm_reg method read_reg. so while doing this read transaction is happening on to the actual bus through agent ,but the I am not getting read value in read_reg task...
View ArticleVCS problem with SystemVerilog
Hi，experts, I am now running into one problem about VCS. Now give a simple descripton about it, I use VCS201209 to compile pieces of verification code, there is no any compiling error，but run time...
View ArticleHow to use a variable defined in one class into another class?
Hello all, Can A variable defined and used in one task, in one class, be used as it is in another class?But these two classes are completely independent of each other,in other words, they are not...
View ArticleHelp in resolving this error?
Hello all UVM geeks, I am getting the following error. Error: monitor71.sv(69): The actual (dataout) and formal (bytestream) for a ref must be equivalent types. Can someone please help me in...
View ArticlePipelined RAL access
I am using UVM RAL (version 1.1c) and with my bus agent which supports pipelined requests and out of order responses. In RAL adapter I have set provides_responses=1. Now when I have two read requests...
View ArticleReturn from function to pass into another function?
Hello all, I want to pass the output of one function (10b8b decoder) into the input of another function viz. drive, where in drive function, I am creating the array out of each byte received from...
View ArticleHow to pass variable sized packed arguments to a task/function?
In SystemVerilog we can have dynamic unpacked arrays and they can be passed to a function/task. I was wondering if there is a way to pass dynamic packed arrays to a function/task. For example consider...
View Articleproblem about variable part select in SystemVerilog
Hi all, I have one problem about variable part select of Verilog. If you know the width, but the upper or lower range is a variable, you can use variable part select. eg : addr[idx_bits-:8] =...
View ArticleAny better way to serialize the data, please give suggestion?
Hello all, I am working on piso(parallel in serial out). I am receiving the 10bits byte properly upto foreach loop, But after that data is not being shifted properly in shift register and its not...
View ArticleHow to deal with sipo task to form the bytes out of it, plz suggest?
Hello all UVM geeks, I am working on SIPO(serial in parallel out) in monitor class. Its not working properly and data is not being shifted in the shift registers. Can someone please guide me how to...
View ArticleTest hang with all objections dropped
Hello, I was wondering if anyone had any ideas on why my test is hanging at the end of the run phase and how to resolve it correctly. The last of the output is listed below. The testbench has a...
View ArticleAny generic method in UVM to find the packet length of incoming packets?
Hello all, I am receiving serial bits in the monitor from DUT. This is RX path and independent from TX path i.e driver path. Then I have to make parallel data out of it using sipo(serial in parallel...
View ArticleHow to use uvm_files to store the packets?
Dear all, In scoreboard, I want to store the received and sent packets into files (byte wise) separately. Can someone suggest how to use uvm_file to do this task? Please give some idea,Thanks
View ArticleHelp on uvm_pw_scoreboard package.
I am using uvm_pw_scoreboard package available on accelera Contributions.I have following queries about it . 1. Why does this package uses uvm_analysis_export and analysis_fifo implementation instead...
View ArticleUVM_ACTIVE data type....bit or int ?
When agents are configured, I typically see something like this: uvm_config_db#(int)::set(this,"testbenchA.masterA_hostB.agentpink","is_active",UVM_ACTIVE); Isn't UVM_ACTIVE of type bit? I see it...
View Articleissue regarding 32 bit crc implementation in transaction class of ethernet...
Hello Friends,I am samrat Patel from ahmedabadCurrently i am working on a project of ethernet packet using uvm methodology.In project i have to implement a 32 bit crc logic in transaction class . i...
View ArticleSequences distribution
Hi , Is there any way to control the sequences distibution on UVM? For example when one would like to give higher probablily to some sequences over the other? Can this be controlled from the test?...
View ArticlePurpose of include_coverage() API in uvm_reg.
I was wondering about the need for the API call include_coverage(...) in uvm_reg. It appears that build_coverage (...) would be sufficient to build whatever coverage is required in the current scope....
View Articlestd::randomize( vs. randomize( vs. this.randomize( and scope
I had expected all 3 of these calls to randomize to return values using the constraint. However, the first does not. Can anyone tell me why? (note: In the following code, there is no local...
View Articleimport statement location effects on random stability
Hi, I'm trying to determine if "import" statements should be within package statements or not, when it comes to random stability.
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