randomize and $dist_normal?
Is there a way to make the randomization of variables via randomize() use one of the different RNGs listed in 20.15 of the IEEE Std 1800 (such as $dist_normal or others)? Or does the use of one of the...
View ArticleHow to respond for a NACK request to resend the frame in UVM?
Hello all, How do I set priorities for some features, to be added in a transaction class? Is there any method in UVM for that? For eg. when I get a NACK, I need to respond to it quickly and resend...
View ArticleQuestasim simulation error?
Dear All, I am getting one strange error while using questasim 10.2a. While simulating 1st time, it simulates properly, all the packages, libraries get loaded fine. But when I tried to simulate the...
View ArticleNesting of frames in UVM?
Hello all, I want to create nested frames/packets. My packet structure is shown below. I want to have nested frames(one or more frames within another frame) starting from 2nd byte of header and...
View ArticleIncompatible complex type usage in uvm
Hi, In my current environment I have monitors class and parametrized scoreboard class. I am sending monitor transaction into scoreboard through the tlm analysis port. Below is snippet of code....
View ArticleSwitching between data_items during simullation
Hi , I would like to use some data items in one test: frame_packet, short_packet , illegal_packet. In the uvm documentation i found that in order to switch between packets i should use factory...
View ArticleStreaming operator for unpacking a bitstream
I'm stuck on a problem I encountered with a use of the streaming operator to unpack into a dynamic array. Rather than write procedural code, I thought I could use it actually with some amount of...
View Article3 TLMs between sequencer and driver?
Hello all, Can I have 3 TLMs connected between a single sequencer and a single driver in UVM? In other words, I want 3 pipes/TLM connections to send three different kind of packets to the same driver...
View Articleconnection between monitor and driver?
Hello All, I need to send some bytes/packets(which are received from the DUT, for eg. NACK for missed packets) to the driver. So can I directly connect the monitor to the driver, without going through...
View Articlecontrol knobs for a driver to be controlled from test class?
Dear All, Is it always the case that the TOP test class can control/manage the control knobs of sequences only? I mean, I want to override/control some parameters of driver class from top test class,...
View ArticleIs it possible to call Python script from SystemVerilog?
Is there any way to call python function from SystemVerilog?
View ArticleSingle transaction class to create different kinds of pkts?
Dear all, I need to create different kinds of packets, for eg nested packets(one or more pkts encapsulated in another pkt), simple packets etc, of the same protocol. Can these different kinds of pkts...
View ArticleMany more sequences in a single sequence?
Hello all, Can there be more than one different kinds of sequences, containing different kinds of pkts, be nested in one single sequence? so that the test case scenerio, will be to show different kinds...
View ArticleHow to generate the even number's and add number's.
Hi all, I have 16 bit data line and in transaction class i declared as "rand". But i want even even number's in one transaction and odd no number's in another transaction. Please suggests me.. Regards,...
View ArticleHow to send some random data in between two packets/frames?
Dear All, I need to send some high impedance/IDLE symbols (eg 101010...) between the two packets/frames for long time. So is it possible in UVM to send some random data (not through packets in the...
View Articleuvm_cmdline_processor get_arg_value/s to receive hex
SPOILER ALERT: I figured this one out, but since I'd already typed up most of the question, here it is anyhow posted to the public domain. Comments welcome....
View ArticleAXI Bridge to ethernet connection
Hi, I've created a UVM model for ethernet 10Gb MAC CoRE. There is a requirement to connect the AXI Bridge to my UVM model. I'm facing severe problems while integrating AXI Bridge to ethernet model....
View ArticleSystemVerilog checkers. simulator support. usage in a UVM environment
Q1) How well do the major simulators support SystemVerilog checkers (1800-2012.pdf Section 17.)? Q2) In (the) UVM, do you think there is a place for checkers? Context) We have VHDL rtl. For the...
View Articlequestion about `uvm_sequence_utils
Does the latest uvm no longer have `uvm_sequence_utils? In the user_guide, seems `uvm_object_utils(seq) is enough to associate a sequence with a sequencer? how does it work? thanks,
View Articlesequence is not running - make sure sequencer name 'correct'
//This is not a question, but me storing some debug notes online, lest I run into this problem again. //good for debugging this issue, print_topology in particular. Put them in your test....
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