Is there a way to override PH_TIMEOUT severity from UVM_ERROR to UVM_WARNING.
I tried using
+uvm_set_severity=uvm_test_top.*,PH_TIMEOUT,UVM_ERROR,UVM_WARNING
in the cmd line, but unsuccessful.
The `uvm_error call is at src/base/uvm_phase.svh(1215)
Can someone help me out please.
Many thanks.
Hi,
I wanted to use the field.mirror() task provided in the uvm_reg_field class to check only a particular field. However, I see that the field.mirror() task is just calling the parent register mirror task. Hence the entire register is read and compared which I didn't intend to do. I tried this in my sequence and I see the above mentioned behavior. This looks like a serious bug. Can you please confirm this.
Regards,
Shreyas
hi, all,
I'm a newer in learning UVM. With the support of many UVM experts, we can find many examples for learnning UVM. However, when I tried to have a taste on some examples using VCS to compile them, the Makefile is a headache for me.
Could you please let me know how to write a good Makefile for compilation and running simulation in VCS?
Thank you in advance!
Liya
As an (unfortunately very) old hand at design and functional verification in VHDL, PSL, UVM/e, C ..... (yawn), and now a few months into SV UVM, I would appreciate people's opinions on coding guidelines. I've read and considered a lot of "macros are/aren't evil" arguments, naming convention "rulebooks" etc, and I'm not concerned with who's right or wrong (too long-toothed to believe there is one). I would, however, like to suck the brains of those of you with more experience and do my best to achieve the following, without endlessly revisiting code to do fiddly edits:
To kick off, what's the thinking on:
James
During the compilation process, my code met two make erros:
make[1]: *** No rule to make target `/proj/verif_release_ro/ovmkit_o2.1.2_u1.1b/14/uvm/src/dpi/uvm_dpi.c', needed by `uvm_dpi.o'. Stop.
make[1]: Leaving directory `.../src/verif/interface/master/examples/master_b2b_test/csrc'
Could anybody tell me what this problem is?
Thank you very much in advance!
Hello All,
I am trying to register my call back class to the register block model for the test bench.
Here is my register call back class.
Suppose I have a 4 port device. Each port in the device has a register object. I want to write a functional coverage model to make sure that I test the registers in each port. I write the following code:
covergroup cg;
myreg_port_0: coverpoint top_reg_obj.port[0].myreg;
myreg_port_1: coverpoint top_reg_obj.port[1].myreg;
myreg_port_2: coverpoint top_reg_obj.port[2].myreg;
myreg_port_3: coverpoint top_reg_obj.port[3].myreg;
endgroup
However, this is not reusable. The next chip planned is an 8-port device. I have to manually modify this coverage model each time the number of ports change. I would like to write the coverpoints using a for-loop to iterate over all the ports.
What is the best way to do this? It doesn't seem possible to use "for" or "foreach" inside a covergroup.
Thanks in advance.
Hi
clocking drv_cb @(posedge clk);
output data;
output sop;
output eop;
endclocking
task rbus_driver::drive_one_pkt(rbus_data trans);
vif.sop <= 1'b1;
vif.deop <= 1'b1;
vif.data <= trans.bytes;
@vif.drv_cb;
end
above is my scenario in this very first data driving starts at negedge of the clk. from second it starts driving from posedge of the clock i don't know why? in the env i have 2 drivers similiar other one driveing perfect from posedge of clk
please any body know why?
I have a UVM TB with a agent to config the registers of the dut. and another 4 agents for packet transaction。
In my test, I have to write the register first and start the packet transaction later on. the code of the sequence look like:
//////////
virtual task body();
`uvm_do_on(my_norm_reg_seq, p_sequencer.reg_sqr); //on clk1
repeat(sent_cnt)
begin
fork
`uvm_do_on(incr_send_pkt_seq_0, p_sequencer.eth_sqr_0); //drvs on clk1
`uvm_do_on(incr_send_pkt_seq_1, p_sequencer.eth_sqr_1); //drvs on clk1
`uvm_do_on(incr_send_pkt_seq_2, p_sequencer.eth_sqr_2); //drvs on clk2
`uvm_do_on(incr_send_pkt_seq_3, p_sequencer.eth_sqr_3); //drvs on clk2
join
end
endtask : body
///////////
if I use all these agents which send the sequence with the same clock, everything is ok.
if I use 2 packet agents and the register agent with clk1, the other 2 agents with clk2, the transaction with clk1 work fine, but the transaction with clk2 is not working.
if I use 2 packet agents and the register agent with clk2, the other 2 agents with clk1, the transaction with clk2 work fine, but the transaction with clk1 is not working.
if I comment out the norm_reg_seq line without configure the register on clk1, the TB will send packet on both clk1 and clk2 in each port correctly.
I doubt if the UVM can switch the clock of the sequences automatically. or is there anything I should tell UVM to do this? does any one really tried to use different clocks for the sequences which executed one after another?
The uvm_event has become a generic class in uvm 1.2, and the default data type is uvm_object. Is this just to stay compatible with existing code, or does it also indicate that the data type is supposed to derive from an uvm_object (or at least be a class)?
Hi,
I remember back in the day in OVM it was possible to say uvm_test_done.set_drain_time(...). With UVM, when compiling with +UVM_NO_DEPRECATED, it's not possible to do this. Phases have their own drain times now. The cool thing about the OVM approach was that I could set the drain time from the end_of_elaboration phase somewhere in my base test and be done with it. I dug around a bit in UVM and found that all phases have singletons. I tried to get a handle to the run phase singleton during the end_of_elaboration phase and set the drain time on that. It didn't work.
All phase methods get a "phase" argument passed to them. I would have expected that this parameter contains already a handle to the phase singleton. I made a small example on EDA Playground (http://www.edaplayground.com/x/2PL) where I get the run phase singleton and print it and also print the argument. They are different objects. Does anyone know what the phase argument getting passed to phase methods is and why it's not the singleton?
Thanks,
Tudor
We've been using UVM 1.1d. Now we're testing 1.2 and after cleaning up some other things we're getting warnings like this:
the name "sso_aw_tb_top.sso_aw_wrapper_i.sso_aw.aw_csr.aq.aq_thr_port" of the component "uvm_test_top.ssoaw_env.mem_env.sso_aw_tb_top.sso_aw_wrapper_i.sso_aw.aw_csr.aq.aq_thr_port" violates the uvm component name constraints
This warning comes from base/uvm_traversal.svh and appears to be from a change put in for Mantis 4712. There's a comment in the Mantis that this was discussed and there was not unanimous agreement to get this into 1.2.
So the first question is this: if this wasn't approved for 1.2, why is it in 1.2?
More important to me is this: is this likely to be approved in the foreseeable future? If it is, we'll clean up our names. If not, I'm inclined to hack the regex to allow dots.
For background info, the vast majority of our object names do not include the full hierarchy. For BIST and ECC testing, we have our memories instrumented to push their full hierarchical name onto a list and from that list we create an analysis port for each one, and the full name is passed in with "_port" when we new the port. We can't just strip it down to the memory name because they're not unique, which is why the full hierarchical name seemed like a good idea at the time.
Thanks.
I am learning UVM. So far I was able to create the following environment for my DUT.
Agents with monitors, drivers and sequences for all of the input-output interfaces from my DUT.
A top level UVM env.
Sequences to send valid data to DUT. I yet to implement scoreboard.
I'm having some trouble to understand how to handle scenarios like following:
For one of my tb->dut interfaces, TB needs to wait for an event (or transaction) from DUT. Once it receives the transaction from DUT, TB needs to send back a response. What is the best way to implement this? How can I monitor DUT transaction from sequence? I assume I need to wait for an event or something similar which will tell me that DUT has a new valid output in its interface.
My agents have monitors which will monitor any new output signals from DUT. So, do I need to somehow bring this data from agent's monitor to my test/sequence class? I know that monitor has an analysis port and it can be used to send received data to scoreboard for checking. So, do I need to use the same port to read DUT output data, create valid response and send it to DUT?
Thanks!
Hi Everyone,
I am using the UVM env, in that I have two agents lets say agent1 and agen2, I want to get the cross coverage of input stimulus generated by both agents.
What I did till now , I have a shared seq_item.svh for both agents , so I did placed the
static cnt = 0;
class seq_item extends uvm_sequence_item;
typedef {x,y,z} lmn_t;
typedef {m,n,o} pqr_t;
rand lmn_t lmn;
rand pqr_t pqr;
covergroup cg_for_agent1:
coverpoint a: lmn;
coverpoint b: pqr;
end covergroup
covergroup cg_for_agent2:
coverpoint a: lmn;
coverpoint b: pqr;
end covergroup
covergroup cg_for_cross_ab;
CROSS_cov: cg_for_agent1.a;cg_for_agent1.b;cg_for_agent2.a;cg_for_agent2.b
end covergroup
function post_randomise();
if (this.get_name == pkt_for_agent1)begin
cg_for_agent1.sample();
cnt++;
end
if (this.get_name == pkt_for_agent2)begin
cg_for_agent2.sample();
cnt++;
end
if (cnt %2 == 0)begin
cg_for_cross_ab.sample();
end
endfunction
Now what I achieved cg_for_agent1 & cg_for_agent2 has bins covered but cg_for_cross_ab received zero bin covered.
Strange how static covergroups lost their value.
Apart from this, the seq_item object is created in both the agents at same time and randomized at the same time.
Please help me where I lost.
Thanks.
P.S: I am also wondering for functional coverage best technique, as per Mentor's guidelines i am doing this to achieve input test stimulus coverage , that i have sent all the vectors, please help me with any example to get it done in some other good way
Thanks again 
What is the easiest way to get my simulation to die upon reaching the first UVM_ERROR?
(I suppose the reporting class could be extended and overridden, or something like that, but if it gets too complicated (as this is not smthg I expect to do much), I'll just temporarily change the offending statements to `uvm_fatals....which is what I just did.)
Is there a built-in switch or define that I can override at the command line?
Do fixed-size arrays not support .size()?
module top;
int farray[10]; //fixed array
initial begin
//1 for (int jjj=0; jjj<10; jjj++) begin //works
/*2*/ for (int jjj=0; jjj<farray.size(); jjj++) begin //doesn't work
//3 for (int jjj=0; jjj<$size(farray); jjj++) begin //works
farray[jjj] = $urandom_range(121,0);
end
$display("******************************");
for (int jjj=0; jjj<10; jjj++) begin
$display("%0d: %0d",jjj,farray[jjj]);
end
end
endmodule : top
Following is the example
class my_sequence extends uvm_sequence...
string file_name;
`uvm_object_utils_begin(mysequence)
`uvm_field_string(file_name,UVM_DEFAULT)
`uvm_object_utils_end
endclass
class basic_test extends from uvm_test
function build_phase(..)
set_config_string("*", "file_name", abc.txt);
endfunction
endclass..
I am passing file_name(abc.txt) from test with set_config_string, but, it is not taking effect.
I did the same thing in driver. it worked well. does UVM supports, overriding local variables in sequence.
Please let me know...
Thanks,
Satya
Hello,
The question is SystemVerilog specific, not related to UVM. I was wondering if it is possible to initialize an interface inside an internal module A and further pass it to an another module B, which is at the same level of hierarchy as the module A.
interface Inter (input logic clk); logic a; endinterface module A(Inter inter); logic clk; Inter inter(clk); endmodule module B(Inter inter); always_ff @(posedge inter.clk) ..... endmodule module top; A a( .* ); B b( .* ); endmodule
Let's assume module A is a master of some Stream interface (like AXI4-Stream), B is the slave. The signal clk could be a regular variable inside the Inter, however, clk must be connected to the interface, so it seems logical to me, that it's on the port list, so developer will not forget to provide it. Therefore (port assignment of inter), the inter has to be initialized inside the module A, not in top as it would be done in case of regular interface usage. The code is for synthesis and my compiler doesn't support virtual interfaces. Does it exist any elegant solution for the described issue ?
Thanks,
Adrian