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Type-parameterized class and callback

January 20, 2014, 12:32 am
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Hi all,

 

There is problem with having callbacks with type parameterized classes:

 

1. Callback class:

typedef class driver;

virtual class driver_cb extends uvm_callback;

virtual task drive(
    driver driver, 
    ref transaction req, 
    ref transaction rsp
);
endtask

function new(string name="driver_cb");
    super.new(name);
endfunction

endclass

2. Class with type parameter:

class driver #(
    type transaction_t = transaction_base
) extends uvm_driver #(transaction_t);

`uvm_component_param_utils_begin(driver#(transaction_t))
`uvm_component_utils_end

`uvm_register_cb(driver#(transaction_t), driver_cb)

function new(string name, uvm_component parent);
    super.new(name, parent);
endfunction

virtual task drive(transaction_t req, transaction_t rsp); endtask

task main_phase(uvm_phase phase);
   `uvm_do_callbacks(driver#(transaction_t), driver_cb, drive(this, req, rsp));
endtask

endclass

typedef uvm_callbacks #(driver, driver_cb) driver_cb_pool;

Compiler claims about type incompatibility and expects that type parameter should be "transaction_base" only.

 

Any help is welcome.

 

 

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constraint solver

January 20, 2014, 10:10 pm
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What is constraint solver in SV? What is the meaning of statement if we say that "SV is having powerful constraint solver"?
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differences b/w ovm and uvm

January 20, 2014, 11:07 pm
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Please brief the differences b/w ovm and uvm or the modifications done in ovm to develop uvm.
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Why is different the declaration class handle before and after the super call?

January 22, 2014, 10:29 pm
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Hi, all

 

   //Case One

class BasePacket;
    int A;
endclass : BasePacket


class My_Packet extends BasePacket;
    int C;
endclass : My_Packet


class BaseTest;

BasePacket PB[string];

virtual function void Create_PKT(string s);
    PB[s] = new();
endfunction : Create_PKT

virtual function void Configure_PKT(string s);  
    PB[s].A = 1;
endfunction : Configure_PKT

virtual function void printP(string s);
    $display("BaseTest::PB[%s].A is %d", s, PB[s].A);
endfunction : printP

endclass : BaseTest


class My_Test extends BaseTest;

virtual function void Create_PKT(string s);
    My_Packet MP = new();
    PB[s] = MP;
endfunction : Create_PKT

virtual function void Configure_PKT(string s);
//  My_Packet mp;
    super.Configure_PKT(s);
    My_Packet mp;  
    $cast(mp, PB[s]);
    mp.C = 2;
    PB[s] = mp;
endfunction : Configure_PKT

virtual function void printP(string s);
//  My_Packet mp;  
    super.printP(s);
    My_Packet mp;
    $cast(mp, PB[s]);
    $display("My_test::PB[%s].C is %d", s, mp.C);
endfunction : printP

endclass : My_Test


BaseTest T1 = new();
My_Test T2 = new();

initial begin
      T1.Create_PKT("StringBase");
      T1.Configure_PKT("StringBase");
      T1.printP("StringBase");
      T2.Create_PKT("MY_String");
      T2.Configure_PKT("MY_String");
      T2.printP("MY_String");
end


//Output Information (Compiler Report Error)
//
//near "mp": syntax error, unexpected IDENTIFIER, expecting #





//Case Two

class BasePacket;
    int A;
endclass : BasePacket


class My_Packet extends BasePacket;
    int C;
endclass : My_Packet


class BaseTest;

BasePacket PB[string];

virtual function void Create_PKT(string s);
    PB[s] = new();
endfunction : Create_PKT

virtual function void Configure_PKT(string s);  
    PB[s].A = 1;
endfunction : Configure_PKT

virtual function void printP(string s);
    $display("BaseTest::PB[%s].A is %d", s, PB[s].A);
endfunction : printP

endclass : BaseTest


class My_Test extends BaseTest;

virtual function void Create_PKT(string s);
    My_Packet MP = new();
    PB[s] = MP;
endfunction : Create_PKT

virtual function void Configure_PKT(string s);
    My_Packet mp;
    super.Configure_PKT(s);
    //My_Packet mp;  
    $cast(mp, PB[s]);
    mp.C = 2;
    PB[s] = mp;
endfunction : Configure_PKT

virtual function void printP(string s);
    My_Packet mp;
    super.printP(s);
    //My_Packet mp;
    $cast(mp, PB[s]);
    $display("My_test::PB[%s].C is %d", s, mp.C);
endfunction : printP

endclass : My_Test


BaseTest T1 = new();
My_Test T2 = new();

initial begin
      T1.Create_PKT("StringBase");
      T1.Configure_PKT("StringBase");
      T1.printP("StringBase");
      T2.Create_PKT("MY_String");
      T2.Configure_PKT("MY_String");
      T2.printP("MY_String");
end


//Output Information
//
//# BaseTest::PB[StringBase].A is           1
//# BaseTest::PB[MY_String].A is           1
//# My_test::PB[MY_String].C is           2

 

 

  I designed two cases as above, ran case one, the simulator reported error as above.

 

  Would like to tell me the different of the declaration class handle before and after the super call?

 

  Thank you in advanced.

 

BR

 

QIN

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configuration object and configuration space in UVM

January 22, 2014, 11:48 pm
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What is the difference between configuration object and configuration space in UVM?
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Accessing arrays

January 23, 2014, 11:53 am
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may I know how the ap aray created in build_phase can be accessed later.

 

   uvm_analysis_port #(req_trans) ap_a[];

 

   function void build_phase (uvm_phase phase);

  

    ..

   ..   

    for(int i = 0; i < num_of_agents; i++) begin

      $sformat(inst_name, "req_agent[%0d]", i);

      m_req_agent[i] = req_agent::type_id::create(inst_name, this);

      ap_a[i] = new($sformatf("ap_a[%0d]",i), this);

    end

 

  function void connect_phase (uvm_phase phase);

    for(int i = 0; i < num_of_agents; i++) begin

      m_req_agent[i].ap_a.connect(this.ap_a[i]);

     end

  endfunction

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Confused between Definitions

January 24, 2014, 4:54 am
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Please I'm beginner in UVM 

 

and I'm confused between two definitions; Agent and Interface UVCs

 

both of them defined as packaging of Sequencer, Driver, Collector and Monitor ,, then what's is the difference ?

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transaction concept in UVM

January 27, 2014, 10:58 pm
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Is there some use of TLM 2.0 concepts in UVM?
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Event Synchronisation from monitor to driver

January 29, 2014, 8:32 pm
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Hello All,

 

My verification requirements demands that whenever monitor senses the byte at serial interface , 

 

then my driver , which is waiting at the event from monitor would be notified, so that it can make necessary decision to wingle the pins(interface).

 

So what would be the solution for that ? and is it a good way ?

 

Thanks 

:)

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UVM in Questasim

February 4, 2014, 12:00 pm
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Can anyone here recommend me chapters needed to read in questasim user guide so as to simulate uvm systemverilog environment ,, let's have assumption that I have no knowledge about simulator commands interface ,,, thanks in advance

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Accessing SystemC from SystemVerilog TB

February 7, 2014, 12:40 am
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Hi All,

I have a basic SystemC TB which has VHDL DUT and some systemC TB components instantiated.

Now I want to build a SystemVerilog UVM TB on top of this systemC TB.

 

1. Is it possible to do this?

2. How to access systemC TB components (like systemC threads, systemC variables & systemC events, etc..) from SystemVerilog TB?

 

Please help to clarify this basic query.

 

Thanks in advance!

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Constraining Sequencer from testcase

February 10, 2014, 9:47 am
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Hi ,

 

Sorry the heading should be Constraint Sequence from testcase

 

I am unable to change it , seen after posted

 

I am wondering to constrain my sequence from testcase, is there any good way of doing it ?

----------------------------Test Code----------------------------------------------\\
class card_test extends uvm_test;

task run_phase(uvm_phase phase);
    card_seq card_seq_i;
    repeat(3) begin
      phase.raise_objection(.obj(this));
      card_seq_i = card_seq::type_id::create(.name("card_seq_i"), .contxt(get_full_name()));
      //assert(card_seq_i.randomize());// actual test case
      //assert(card_seq_i.randomize() with { card_seq_i.pkt_state == READY;}); // dedicated test
      `uvm_info("card_test", { "\n", card_seq_i.sprint() }, UVM_LOW)
      card_seq_i.start(card_env_i.card_agent_e.m_sequencer);
      #10ns ;
      phase.drop_objection(.obj(this));
	end
   endtask: run_phase

The line 09 and 10 if chosen gives me error.

 

Thanks for help

 

Regards,

KS 

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Functional Coverage: How to sample RTL signals in a hierarchy (gives error)

February 13, 2014, 2:33 am
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Hello,

 

I am creating a functional coverage model.

I am binding my coverage model with the design using the "bind" statement.
I need to access some internal signals of a design instance inside a design module for using in my functional coverage model. However I get an error when I try that.

 

Below is what I am trying =>

In the RTL design module "dut_berc", there is a instance "dut_berc_cmd". I need to access the signal "pct_err_status_vec" in this "dut_berc_cmd" module.

 

So in design =>
-----------------------------
module dut_berc #(....)
(clk, reset, ....
);

dut_berc_cmd #(...)

       u_dut_berc_cmd (..);
-----------------------------

-----------------------------
module dut_berc_cmd #(....)
(.....
);

 

logic [PCT_DEPTH-1:0] pct_err_status_vec; <----- This is the signal I need to sample inside my functional coverage model

-----------------------------

 

In the top level TB file, the bind happens =>
---------------------------
bind dut_berc
dut_cov_berc #()
FUNC_COVERAGE (.*);
---------------------------

 

In "dut_cov_berc" =>
-------------------------
module dut_cov_berc #(...)
(
input [PCT_DEPTH-1:0] u_dut_berc_cmd.pct_err_status_vec,
........
)
-------------------------

 

However I get the following error when I try this =>
-----------------------------------
** Error: /view/....../src/dut_cov_berc.sv(36): near ".": syntax error, unexpected '.', expecting ')'
-----------------------------------

 

I tried directly accessing the signal in my functional coverage module but it gave an error that it is unable to find this signal.

Please let me known what is the correct way to access design signals present in a hierarcy in the functional coverage model?

 

Thanks.

 

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Polymorphism in testbench

February 14, 2014, 3:01 am
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Where is the use of the concept of polymorphism in testbench development in UVM. Please tell me some usecases of polymorphism in testbench development.

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8b10b function

February 17, 2014, 9:20 am
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I need to implement 8b10b encoding and decoding functions in a serial UVC I am developing. However, I am unsure of the best method to use to apply the 8b10b coding algorithm. My first thought was to create a set of 8b10b encoding/decoding tables using a struct, pass the generated bytes/characters into the tables, and continue using the resulting value in the transactions. However, this doesn't seem to be the most efficient method to use.

 

I've never found or seen a canned set of 8b10b libraries to use, so I need to roll my own. If anyone has done this before and could get me pointed in the right direction, please let me know.

 

Thanks!

Tony

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How to use UVM Sequencer with e-based driver

February 18, 2014, 2:28 am
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Hello All,

 

I am wandering if I could use the edriver with UVM sequencer.

 

 

Please help me by providing some clues.

 

Thanks, 

Karandeep

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Multithread and automatic variable

February 24, 2014, 10:53 am
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Hi , 

For below code , for case-1 and case-2 output is different ,

 

module my_module; 
    int a=0; 
    initial 
    begin 
      for(int i=0;i<5;i++) 
      begin     
         fork 
                // Check differance here , between 2 statements 
                // ##case 1 (declaration and assignment). automatic int j= i;
                // and 
                automatic int j;  // ##case 2 declare 
                j=i;                  //  then assign
                begin
                    $display("Chk auto %d",j);
                end    
         join_none  
      end
    end 
endmodule : my_module

 

For case-1 output is  0 1 2 3 4 

 

For case-2 output is 5 5 5 5 5 

 

Can anyone explain me how??

Thanks , 
Parth

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When a phase completes, are any lingering processes terminated?

February 26, 2014, 4:55 am
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Q1) If I use a fork-join_none to spawn a process in a phase, and then that phase ends (b/c objection is dropped), is the process terminated or allowed to complete?
 
 
I seem to be seeing that the process is terminated (but was expecting that it would be allowed to complete) and wanted to confirm that this is the expected behavior.  
Q2) Where is this behavior best documented?
 
 
(Context: I was moving my timeout-timer from main_phase to pre_reset_phase, so that its time begins at time==0.  If processes are killed when a phase ends, I suppose I should move it to run_phase to align it with time==0, ..... or start using the heartbeat component, which I have not gotten around to doing yet, but have been thinking a lot about.)
 
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Difference between uvm_hdl_force and uvm_hdl_deposit

February 26, 2014, 10:45 pm
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Hi all,

 

What exactly is the difference between uvm_hdl_force and uvm_hdl_deposit? The UVM Class reference document doesn't provide much explanation. Please help.

 

Thanks,

Shreyas

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IP level and SOC level Verification

February 27, 2014, 2:36 am
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What are the differences in IP level and SOC level Verification? Which kind of difficulties we face in SOC level Verification as compared to IP level verification?
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