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View Articlehow to use uvm reg callback to implement reg_a read being qualified by a...
Hi, I have implemented a uvm reg block containing several uvm reg's. What I want to model is register reg_a has the following layout: {fld_a, fld_b,fld_c} and register reg_b has: {fld_st,fld_rsv} The...
View Articleiff usage (as a mechanism for waiting)
I happened across the following code. @(m_vif.smp_cb iff (m_vif.smp_cb.xyz_enable) ); To get to the crux of my question, let's consider it to be the below code. I don't think I've dropped anything...
View ArticleSC_FIXED and UVM ML Packer
Hi, I am trying to use SC_FIXED in a UVM ML environment, but the uvm_packer.h doesn't support sc_fixed. virtual uvm_packer& operator << (bool a); virtual uvm_packer& operator <<...
View ArticleHow to get virtual interface in sequence
HI Can any one provide some example for how to get virtual interface in sequence? I need to use the clk in sequece . Thanks praneeth
View ArticleParameterized interfaces
a usual way to do it is to create a wrapper object and push the wrapper into config_db. Then get this wrapper object from config_db and assign it to the virtual interface pointer (not mentioning the...
View Articleuvm_resource_db usage
Hi, I am using uvm_resource_db to set and get any component configuration. But I am getting an error saying configuration object is not found. Its something that its not able to get the config object...
View Articlemember reference resolution error related to uvm_analysis_imp_decl
Hi, I am seeing member reference resolution error related to uvm_analysis_imp_decl. Linenum52:`uvm_analysis_imp_decl(_mon).Please see in below code. You can see the error as well below which got...
View ArticleBug in SV LRM
Sorry for posting this here, but I can't figure out how to log in to or register for the SV Mantis, so I hope posting here will get to some of the right people... In table 22-2 in 1800-2012, the...
View Articlebus monitoring : Using SVA to pass transactions to monitor?
I have a SV interface which hangs off a bus, waiting for transactions to occur. I use SVA to look for sequences, and verify correct protocol. Each of these SVA constructs have implication operators....
View ArticleUVM -Control an interface pin from different agents
Hi all, I'm doing verification for an PHY between SPI master and a memory chip. I make two agents one for master to transfer the request, one mimics the memory slave to reply. PHY will be hooked up...
View Articleuvm_sequence_base kill on virtual sequence
When using uvm_sequence_base's kill on a virtual sequence, will it kill child sequences? It seems to me that it will not, but I am unsure and have not explored this much, yet. Looking briefly at the...
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