Hi,
I have implemented a uvm reg block containing several uvm reg's. What I want to model is register reg_a has the following layout:
{fld_a, fld_b,fld_c}
and register reg_b has:
{fld_st,fld_rsv}
The read return of reg_a has fld_b and fld_c as is, while the fld_a value of read data is dependent upon the value of reg_b.fld_st:
If reg_b.fld_st = 0, the read data of reg_a is {0,fld_b,fld_c}
If reg_b.fld_st = 1, the read data of reg_a is unmodified.
I think I need a post_read task implemented for reg_a, but could you please let me know where I should put it?
The scope of accessing both reg's should be at reg block, but I don't know how to add a callback there to achieve this.
An example is much appreciated.
Thank you.
I have implemented a uvm reg block containing several uvm reg's. What I want to model is register reg_a has the following layout:
{fld_a, fld_b,fld_c}
and register reg_b has:
{fld_st,fld_rsv}
The read return of reg_a has fld_b and fld_c as is, while the fld_a value of read data is dependent upon the value of reg_b.fld_st:
If reg_b.fld_st = 0, the read data of reg_a is {0,fld_b,fld_c}
If reg_b.fld_st = 1, the read data of reg_a is unmodified.
I think I need a post_read task implemented for reg_a, but could you please let me know where I should put it?
The scope of accessing both reg's should be at reg block, but I don't know how to add a callback there to achieve this.
An example is much appreciated.
Thank you.