I just wonder if it is possible to override a build phase from uvm_driver? Seems there's only way is to override driver type/instance, but not phase.
thanks,
Jennifer,
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override UVM phase?
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"Mixin" classes - parametrizing the base class
Hi UVM and SystemVerilog users,
I've stumbled upon a particular pattern of writing a "utility" class, which I have called "mixin".
class derived_class#(type BASE=base_class) extends BASE;
....
endclass : derived_class
This pattern was inspired by some C++ Boost code I saw, where the base class is templated. The reasoning was that under some compilers, multiple inheritance had higher overhead than chains of inheritance (specifically, an "empty" base class might be allocated the minimum size, so multiple inheritance would increase the size of the object, but if you used a chain of inheritance and a derived class in the chain was "empty" (i.e. did not add any data members), it would not increase the object size). So instead of inheriting from multiple C++ classes, you'd typedef a class like foo<bar<nitz> > and derive from that.
Since SystemVerilog has no multiple inheritance, I thought this pattern would be appropriate for use in SV, to at least ease some of the "oh no SV has no multiple inheritance oh no" pain.
I've defined a simple utility class, utility::slave_sequence_item (utility is a package) defined like so:
class slave_sequence_item#(type BASE=uvm_sequence_item) extends BASE;
local uvm_barrier wait_barrier_;
local uvm_barrier fin_barrier_;
`uvm_object_param_utils_begin(utility::slave_sequence_item#(BASE))
`uvm_field_object(wait_barrier_, UVM_ALL_ON)
`uvm_field_object(fin_barrier_, UVM_ALL_ON)
`uvm_ojbect_utils_end
function new(string name="");
super.new(name);
wait_barrier_ = new("wait_barrier_", 2);
fin_barrier_ = new("fin_barrier_", 2);
endfunction
// to be called by sequence
task wait_for_transaction;
wait_barrier_.wait_for;
endtask
task finish_transaction;
finish_barrier_.wait_for;
endtask
// to be called by driver
task indicate_transaction;
wait_barrier_.wait_for;
finish_barrier_.wait_for;
endtask
endclass : slave_sequence_item
Basically, this slave sequence item class adds three new methods. By default, you just derive from utility::slave_sequence_item. But if you already have an existing sequence item type derived from uvm_sequence_item, you just do typedef utility::slave_sequence_item#(my_sequence_item) my_slave_sequence_item; and the added methods and variables will get "mixed in" the my_slave_sequence_item type.
What do you think?
I've tested it on Cadence IUS10.20-s103, and it seems to work properly. From my understanding of the IEEE standard, the above is not specifically disallowed (but then it might not be well supported on actual simulators).
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print internal variables of property in sva
Hi ,
Could you please help me on how to print or display internal variables of property used in sva
Regards,
Pavan.
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who can interpret use of soft constraint ?
Hi,I have such a question
https://verificationacademy.com/forums/uvm/how-use-soft-constraint
who can help me ?
thanks
/wszhong
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How to do multiple writes using uvm_hdl_force
Hi,
I my using uvm_hdl_force("path",data) to configure the registers of the design. But the problem is they are large in number so i want to loop them in.
for(int i=0; i<8; i++) begin
for(int j=0; j<8; j++) begin
uvm_hdl_force("DUt.abc.pkt.reg_0.w[1]" , data);
end
end
I want to replace 0 with i and 1 with j . Is their a simple way to do it.
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How to override set_timeout
Hello All,
Please help me :
I have different tests requiring different timeouts, let say:
1. Test1 - timeout 100ns
2. Test2 - timeout 100ms
3. Test3 - timeout 1s
In the test base I have set_timeout(1000ns, 1) , so how to override this timeout from various tests
or any other way to achieve this , unfortunately unable to finad any good example to understand 
-Thanks
Karandeep
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Pointer passing across multi-language boundaries - SC<->SV
Hello All,
A professional collegue asked me this question today, at that time I missed to answer.
But assured him that we will discuss this over accellera.
So the answer is UVM_TLM_GP, it is using pointers that can be well passed over the language boundary.
P.S: I wish this is the question , if not please feel free to update the query.
Cheers,
Karandeep
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Can we perform UVM_REG read/write access based on Address?
Hi there
From the UVM users guide, a register read access can be executed as
reg_model.BLK1.REG_FILE1.REG_1.read(status, rdata);
But this mandates us to know the hierarchy of the register instantiation.
ie., 'reg_model.BLK1.REG_FILE1' needs to be known to execute a read on register 'REG_1'.
Is it possible to perform read/write access based on address instead of this hierarchy?
Something like:
generic_uvm_read (.address(0x0), rdata);
In otherwords, we need not even know the register type or register instantiation hierarchy to issue a read access to that register.
Can this be performed with UVM_REG?
Requesting thoughts here.
Best regards
Balasubramanian G
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uvm_tlm_analysis_fifo issue
Hello All,
I am facing a acute problem:
Using a uvm_tlm_analysis_fifo as:
class bla_bla extends uvm_component
uvm_tlm_analysis_fifo (my_packet) analysis_fifo;
my_packet get_my_packet ;
// other code
task run_phase
for(int i = 0 ; i < 10; i++)begin
analysis_fifo.write(my_packet<updated everytime before this>);
end
for(int i = 0 ; i < 10; i++)begin
analysis_fifo.get(get_my_packet);
get_my_packet.print();
end
this displays last packet value always 
I have made a small test and created it for int type instead of using the packet and it works fine with it, may be I am missing something
What should I need to do get the right values.? Is there any issues that it is keeping the pointer to the value written and one has to maintain that packets himself ?
Note: the above is just an example of the problem I am facing , since the exact code is much bigger so created an example just to explain better, it may have some syntax issues.
Thanks,
Karandeep
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uvm_hdl_force error
Hi,
While doing force using "uvm_hdl_force", i am getting the below error and the specified memory location is not written with that value.
But it works using "force". Any solution to this.
ERROR: VPI NOFORCO
vpi_put_value() cannot force object of type: vpiReg.
Thanks
QW
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uvm reg limitation
Hi,
I there a limitation to the number of registers that can be handled by uvm register model?
if yes, whats the count.
QW
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Is there any obligation in using dynamic delay while starting the sequences
Hello All ,
I am wandering that why virtual sequence not allowing me to implement delays :
Consider the following three cases -
1 .
//-------------------------------------------------------------
// This virtual sequence does SPI boot default
// ------------------------------------------------------------
class sfc_default_boot_vseq extends sfc_seq_base;
`uvm_object_utils(sfc_default_boot_vseq)
//----------------------------------------//
// Data Members //
//----------------------------------------//
rand int delay;
int delay_p;
//----------------------------------------//
// Typedef //
//----------------------------------------//
rand enum {ZERO,SHORT,MEDIUM,LONG,CRITICAL} delay_t;
//----------------------------------------//
// Contraining the delay //
//----------------------------------------//
// Contraint on delay
constraint c_delay{
(delay_t == ZERO) -> {delay == 0};
(delay_t == SHORT) -> {delay inside {[1:500]}};
(delay_t == MEDIUM) -> {delay inside {[1000:2000]}};
(delay_t == LONG) -> {delay inside {[2000:50000]}};
(delay_t == CRITICAL) -> {delay inside {[19000:22000]}};
}
// Contraint on weightage
constraint c_dist{
delay_t dist { ZERO := 4, SHORT := 1, MEDIUM := 1, LONG := 1, CRITICAL := 2};
}
////----------------------------------------//
//// Post Randomize //
////----------------------------------------//
function post_randomize();
delay_p = delay;
// Coverage generation
default_boot_delay_cov.sample();
endfunction
function new(string name = "sfc_default_boot_vseq");
super.new(name);
endfunction
task body;
// Sequences to be used
sfc_default_boot_seq default_boot_seq = sfc_default_boot_seq::type_id::create("default_boot_seq");
super.body;
begin
repeat(10)begin
if(!this.randomize() with {delay_t == SHORT;})begin
`uvm_error("VIRTUAL SEQ", $sformatf("Randomization error for CDM seq selection"))
end
default_boot_seq.start(m_t3_sequencer);
$display ("JUST_CHECK: value of delay_p in default_boot = %d",delay_p);
#(delay_p*1ns);
end
end
endtask
endclass: sfc_default_boot_vseq
2. Making all this delay processing as a seq_item class and randomizing that class here only and getting its delay variable.
repeat(10)begin
if(!system_delay.randomize() with {delay_t == SHORT;})begin
`uvm_error("VIRTUAL SEQ", $sformatf("Randomization error for CDM seq selection"))
end
default_boot_seq.start(m_t3_sequencer);
$display ("JUST_CHECK: value of delay_p in default_boot = %d",delay_p);
#(system_delay.value*1ns);
end
3. Using static delay #1000ns
repeat(10)begin
if(!this.randomize() with {delay_t == SHORT;})begin
`uvm_error("VIRTUAL SEQ", $sformatf("Randomization error for CDM seq selection"))
end
default_boot_seq.start(m_t3_sequencer);
$display ("JUST_CHECK: value of delay_p in default_boot = %d",delay_p);
///#(delay_p*1ns);
#1000ns;
end
No. 3 works only for me , can you please tell where is problem in others , since getting the printed value of delay fine in case of 1 and 2. Why can't I use dynamic or constrained random delay over here. What can be the possible alternative.
Thanks ,
Karandeep
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Configure DUT ports from outside agent
Hi All,
I am learning UVM at the moment and I am working on an I2C slave monitor. I want to put multiple I2C slaves on a bus, each slave will have a dedicated agent. One of these agents will be active - driving transactions to the across the interface. Each slave should access the bus by driving SDA at any one time.
I wish to put a monitor on the SDA line, such that any time it is driven by a slave (not the master) - a check that the slave was previously addressed can be performed. Part of this check requires information on pins from the DUT (SDA_out, slave_address[x:y]). How can I get this information into the monitor of each agent without hard-coding the values?
Thanks,
S
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uvm_send is blocked even after driver executes item_done
Hi All,
I have a sequence sending a created and randomized item using `uvm_send.
The driver receives an item using try_next_item. Upon receiving, it drives the item and calls item_done.
Using debug message after item_done, I can clearly see that item_done is called and returned but `uvm_send in sequence is still blocked and not doing forward to send next item (it implements a loop).
Can anyone help me with possible reasons why `uvm_send would not return even when driver has called item_done and come out of item_done.
Thanks in advance!
Ninad
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How to use SVA check different clock delay
Hello,
I would like to check tiny delay b/w clk1 and clk2.(delay inside [1.2ns : 3.2ns]).
Can this kind of check be implemented by SVA?
How record 2 timestamp in one property?
@(posedge clk1)(1,tag1=$realtime)
@(posedge clk2)(1,tag2=$realtime)
I review the SV 1800-2012 spec, there are some timing-check tasks. e.g. $setup, $hold, $timeskew ...
Are these tasks available in property?
$timeskew(posedge clk1, posedge clk2, delay_max,,,1);
$hold(posedge clk1, posedge clk2, delay_min);
Thank you,
Meng
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how do we sort the UVM_REG space based on address?
Hi there
We want to traverse through all registers present in a UVM_REG_BLOCK based on increasing address.
We have the following pseudocode:
model.NTB_DB.get_registers(total_regs_ntb);
foreach (total_regs_ntb[i])
begin
total_regs_btb[i].write(status, wdata, .parent(this));
end
But, the above source code does not go through the registers space based on address.
ie., When I have a 2-dimensional array of registers, array indices are chosen first(not addresses).
Any help to workaround this problem is appreciated.
Best regards
Balasubramanian G
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conditionnal import package in SV
Hello everyone,
I want to select package depending of parameter. I have the same parameters which different value in this two packages : pkg_std, pkg_a. And I would like to select the good one depending of the mode A
I don't know if it's possible.
Modelsim get an error on this :
Parameter A = 0;
if(!A)
begin
import pkg_std::*;
end
else
begin
import pkg_a::*;
end
It s seems a conflict between the two packages, because all parameters declared into the package are "undefined variable".
I'm curious if you have already to attempt this?
Let me know, please.
Thanks a lot.
Bye, JP LM
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SystemVerilog connecting a channel
I'm trying to hook up a new channel (channel 2) to an existing one (channel1) like so:
channel channel1;
channel channel2;
extern function new(
channel_type channel2
);
function subenv1::new(
channel channel2
);
this.channel1 = new();
xactor1(
this.channel1
);
xactor2(
this.channel1
);
//channel1 is a connection between both xactors
//hook new channel2 up to channel1
channel2 = this.channel1
This seems to work fine at this level, ie if I do this check, it doesn't cause a fatal:
if (channel2 ==null) `cvm_fatal
However when I go up to the subenv above this
if (channel2 ==null) `cvm_fatal
Then I get a fatal. What else do I need to ensure that the channel is not fatal at the next level up?
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Rnadomize a variable inside a function
Hi,
I want to randomize a variable defined in a function. The function is inside a package.
I tried declaring a class inside the package and taking the instance of that class in the function.
But that didnt work out as the object needs to be static.
I tried randomization() function, but the problem is the variable "k" can only have 2 value ie (5,9).
function foo()
int k;
void'(randomize(k)) with {k==5;k==9;}); // I am getting randomization failure in this case.
endfunction
Let me know how can this be resolved.
Thanks.
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Using $past in procedural code
Hi everyone,
I'm not sure if this is the right place to post this. I have question regarding the usage of $past(...) and the other members of that family inside procedural code. The SV 2012 standard says the following: "The use of these functions is not limited to assertion features; they may be used as expressions in procedural code as well."
I've tried using a call to $past(...) with an explicit clocking event inside a class task. One of our simulators complained that this is only allowed in assertions and procedural blocks. The other one we use allows it. The standard is rather vague here. What constitutes procedural code? Hopefully someone from the SV Committee hangs out in this forum.
Here's the code I'm trying.
module top;
bit clk;
bit some_signal;
always #1 clk = ~clk;
class some_class;
task some_task();
bit foo;
foo = $past(some_signal,,,@(negedge clk));
$display("some_signal was %b at the last negedge", foo);
endtask
endclass
initial begin
automatic some_class obj = new();
@(posedge clk);
some_signal <= 1;
@(negedge clk);
some_signal <= 0;
@(posedge clk);
obj.some_task();
$finish();
end
endmodule
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