Using DPI-C sin function
Hi, I'm trying to use DPI-C to import sin function, but it doesn't work, as a workround i had used a sin approximative function which finally give a static value of 2.5 (the offset value) i think...
View ArticleIssue with add_hdl_path (peeking two sub modules regsiters)
HI I have two sub modules called A and B within DUT and trying to get register information of both A and B in back door using peek method. I have single ral block which includes both A and B...
View Articlevirtual sequencer exit main phase prematurely
hi all, my SPI test stuck and test sequence is hung on wait_for_grant(). I turned the verbosity to UVM_DEBUG and found out virtual sequencer and physical sequencer exit from main phase and...
View ArticleSVA for fairness of Round-Robin Arbiter
Are are any standard or recommended ways of verifying the functionality of the round-robin arbiter and more specifically checking the fairness? I'm looking for something that is scalable with the...
View Articlerandomize() with inside syntax
How can I use "randomize() with" along with "inside", on the same line? Below is some code that solves the problem using >= and <=, but I'd like to use "inside". module top; class aclass;...
View ArticleUVM Phases: end_of_elobration
I referred couple of documents; cookbook, uvm 1.2 user guide, to know why end_of_elobration is required. However, i could not find answers for 'why it is required' and more specifically 'Is it...
View ArticleWhy we get SEQREQZMB when jumping to another phase
I have a reset sequence, which starts as default_sequence for reset_phase. For main_phase I have some sequence, which is started as default sequence. At some time I jump from main_phase to reset_phase....
View ArticleInstance override RAL adapter transaction objects?
Hello, We have a test bench environment where we have 2 objects of the same SPI env class. The SPI env sets the sequencer for the RAL model as follows:...
View Articlestring literal spanning a newline (using a backslash) - vendor supported?
A backslash can be used to extend a string literal onto the next line if "the new line is immediately preceded by a \ (backslash)." Section 5.9 of 1800-2012.pdf, the SystemVerilog LRM I don't...
View ArticleQuery related to UVM_RAL_REG model.
I have query related to UVM_RAL model. Does it support for case-insensitive for accessing Registers and Register fields items from UVM_RAL model? For example. We have testcase with extension of...
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block level verification in a system setting
Let's say I have the following DUT. The UVM environment contains a chain of models/predictors. Input data flows down this chain and generates the expected CHIP output, which is compared to actual....
View ArticleImproving transaction recording
I am trying to improve transaction recording. So far we have used field automation macros, but to make debugging efficient I am trying to customize the recording. I've understood that the do_record...
View Articlewaiting for next clk edge, interfaces and clocking blocks
Q1) I'd like confirmation that the following waits for a posedge of clk are identical. (The code it refers to is far below.) 1) @(posedge my_play_if.clock); or @(posedge clk); 2)...
View ArticleRAL mapping reg_field to another reg_field
Hey! I'm think need some help with RAL. I have 2 registers and in reg A field F1(RO) mapped from reg B field F1(RW) how i must implement this using RAL?
View ArticleCommunication between uvm_sequence and uvm_component
I have two classes, one is block_seq which extends from uvm_sequence and other is block_cfg_mngr which extends from uvm_component. How do I exchange information between these two. I need to generate...
View ArticleTurn off `uvm_info messages
Is there any way to turn off `uvm_info messages being displayed on the log while retaining `uvm_error and `uvm_fatal messages
View ArticleUnique array elements without rand or randc
I have a variable logic [31:0] id which is not declared as rand or randc. I need different id's each time into an array logic [31:0] id_array [16].logic [31:0] id;logic [31:0] id_array...
View Articlenon-uvm message compliant, grep during report pahse.
is there way to search for the non-uvm compliant error message such as "ERROR - CSI Rx BFM " during the uvm report pahse of uvm environment? if we see this string error count variable need to be...
View ArticleIs it possible to have two implementation of b_transport?
I need to have two uvm_tlm_target_socket in a class and I need to do different set of things with the data received via two sockets. I was thinking if it is possible to have two implementation of...
View Articleconfig_db usage: base class versus derived class objects
Is it possible to do a uvm_config_db::set() for an object of derived class type using the base class handle and later do a uvm_config_db::get() of same object using the derived class handle...
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